FPGA rivals continue to play ‘follow the leader’
The reason, and perhaps importantly, is that Xilinx’ device uses four identical dies connected using a silicon interposer; a ‘2.5D’ multichip approach, while Altera’s is a monolithic device.
The difference may be significant, as while using a silicon interposer may allow a greater number of transistors to be integrated in to a single device, it will inevitably introduce a new complexity not present in monolithic devices. The process has been developed in association with TSMC and Amkor Technology, with some input from Ibiden.
Xilinx admits the technology could be adopted by its competition, but insists that it needs the right architecture to take full advantage of the benefits. The technology was introduced about a year ago, but the story goes back further; to around five years ago when Xilinx introduced its ‘slice’ approach to creating FPGA architectures. This achievement may go some way to vindicating that move, which at the time was questioned by its competition and the industry.
Using a 2.5D approach may be the only way of actually integrating that many transistors in a single device, and noticeably Xilinx is using TSMC’s HPL (high performance, low power) 28nm process, while Altera appears to have opted for the 28HP (high performance) variant, which will likely give the Stratix V a performance benefit but at the cost of increased power dissipation.
With nearly 4 billion transistors on a single substrate, that could be pushing the proverbial envelope. While figures haven’t been released by Altera, Xilinx is clearly targeting low to medium complexity ASICS with the 2000T family, which incidentally it claims breaks another industry trend by delivering the highest performing member of a family while only being the second device to be released. Normally, the highest performing members aren’t released until the family is well established and the process well understood.
Despite integrating such a large number of transistors, the equivalent ASIC gates is still ‘only’ 20 million, which is around 2 million logic cells. This represents about one third of the total transistors implemented across the four identical silicon ‘slices’, showing that, today, the majority of transistors are needed to support ancillary functions, I/O, memory and other hard-wired IP in a high-end FPGA.
However, Xilinx maintains that developing an equivalent ASIC would incur NRE costs of around $50 million, which would need the OEM to sell relatively high volumes of the IC in order to recoup costs and return a profit. In today’s industry the trend is the opposite; lower volumes. While it is a trend that FPGA manufacturers have used since inception to sell their wares, the inexorable increase in FPGA densities must indicate that the returns are there to be had, most notably in markets that are fast moving.
The two end-applications Xilinx cites for the 2000T – which arguably demonstrate the right market dynamics rather the technical complexity – are wired communications and storage area networks. Xilinx further justifies the technology by pointing out that the benefits in power, bandwidth and latency with compared to multi IC solutions (several FPGAs) is an order of magnitude; a single FPGA may offer 1000 I/O to connect discrete devices, while the silicon interposer offers 10,000 interconnects between dies. However, the company concedes that OEMs would face similar challenges if they were to use multiple 2000T devices, so the density is crucially pitched to replace low to medium complexity ASICs with a single FPGA.
While the 2000T is a homogeneous device (four identical FPGA slices), the next device will be heterogeneous; different dies in a single package. That is likely to be Virtex 7 HT family, and following that the company says it will also be adopting a full ‘3D’ approach.
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