FPGAs use transcoding to reduce bandwidth cost in video streaming
COVID-19 has turned a lot of people onto video streaming. However, it just accelerated an already growing trend. Streaming video is being used for all sorts of things, including live game streaming. Increased bandwidth and low latency are making video streaming very desirable, but bandwidth equals cost. To save money, bandwidth requirements can be reduced through transcoding. Xilinx has an answer.
Transcoding essentially converts data of some input format to an output format. Typically, this is done to compress video so that, say, a 4-Mb/s input stream scales down to 2.8 Mb/s. If the monthly cost of a gigabyte-per-second is $0.05, then 100K stream compressions will result in a cost savings of $21 million.
The Xilinx Real-Time (RT) Server reference design targets the video-streaming space (Figure 1). The High Channel Density Video Appliance version contains up to eight Alveo U30 FPGA accelerator cards, while the Ultra-Low Bitrate Optimized Video Appliance integrates up to eight Alveo U50 cards.
The web-based interface allows for system management without dealing with the FPGA code. Xilinx integrated the Wowza Streaming Engine media server with the Xilinx RT Server Reference Architecture. The system uses the FFmpeg framework that’s compatible with other platforms that utilize CPUs or GPGPUs to handle transcoding chores. The HEVC codec was built from the ground up with emphasis on improved codec control down to the frame level. System integrators can adjust rate control and fine-tune other parameters to improve video streaming quality and bitrate to suit their customer’s needs.
Supporting numerous different streams is important due to the rising level of live broadcasts (Figure 2). Less transcoding is needed if a small number of streams will be watched by many people. At the other extreme is a large number of streams for a small group or an individual.
The delivery of an appliance is a big change for Xilinx that started with FPGA chips. These have become more integrated with SoCs like the Zynq, which combine CPUs with FPGA fabrics. The RFSOC family blends high-speed RF support into the mix. The adaptive compute acceleration platform (ACAP) even adds machine-learning acceleration.
It has recently moved into FPGA cards for the data center with the Alveo line, which is the basis for the Xilinx RT Server.