Fraunhofer, Achronix team for chiplet demonstrator

Fraunhofer, Achronix team for chiplet demonstrator

Business news |
By Nick Flaherty

German research institute Fraunhofer IIS/EAS is working with embedded FPGA developer Achronix Semiconductor on a heterogeneous chiplet demonstrator.

Fraunhofer provides system concepts, design services and fast prototyping in most advanced packaging technologies and will use of Speedcore eFPGA IP from Achronix in its next project. The multi-chip system solution will be composed of several chiplets to explore different chip-to-chip transaction layer interconnects such as Bunch of Wires (BoW) and Universal Chiplet Interconnect Express (UCIe) and validate performance and interoperability in advanced high-performance systems.

Achronix has been aiming the eFPGA technology at chiplet designs since 2018, working with NXP and Meta.

One key application that will be covered in this project is the connection of high-speed ADCs together with Achronix eFPGA IP for preprocessing in radars as well as wireless and optical communication. The Speedcore eFPGA IP is playing an important role in this application with low latency and reconfigurability while delivering high-performance data acceleration required in many applications.

The result of this project will create a demonstration platform suitable for applications such as 5G/6G wireless infrastructure, ADAS and high-performance test and measurement equipment.


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