Free verification IP helps drive RISC-V SoC designs
Imperas Software in the UK has added key elements to its RISC-V processor hardware design verification tools that it says will help the development of system-on-chip devices.
The release includes an enhanced reference model with SystemVerilog encapsulation / integration and new test bench blocks, a new riscvOVPsimPlus free simulator and a range of RISC-V architectural validation tests for the ratified and soon to be ratified RISC-V ISA extensions.
“The open standard ISA of RISC-V is enabling system designers to explore new innovations with optimized processors, which in turn is driving all SoC adopters to expand the design verification plans to cover the specialist processor DV tasks,” said Simon Davidmann, CEO at Imperas Software Ltd. “We are proud of the success the Imperas RISC-V golden reference model has achieved and see the new Verification IP and test suites as a way to help all SoC teams address the challenges of processor DV through the adoption of SystemVerilog test benches with step-and-compare methodologies for processor DV.”
The riscvOVPsimPlus RISC-V reference model and simulator has been widely adopted across the RISC-V verification ecosystem and has been updated and extended with additional features including full configurable instruction trace, GDB/Eclipse debug support, plus memory configuration options. The updated model includes all the full standard CLIC features, Debug Module / Mode, “H” Hypervisor simulation, and also ‘near-ratified’ ISA extensions for Vector “V”, Bit Manipulation “B”, and Crypto (Scalar) “K” extensions.
To support the SystemVerilog encapsulation of the reference model, the RISC-V Processor Verification IP (VIP) package includes example SystemVerilog supporting components and modules for interfacing and synchronization between the Imperas RISC-V golden reference model and the RTL core under test in a step-and-compare verification flow.
This approach covers the important aspects of asynchronous events and debug mode operation while also supporting the DV engineer’s active investigation directly at the point of interest during test failure analysis and resolution.
Coverage is a key aspect for any verification plan, as it helps measure the progress toward the quality targets for design completion and tape-out milestones. To support instructional and architectural functional coverage the Imperas RISC-V golden reference model has been further enhanced with built-in monitors to provide coverage metrics without the need for post-simulation processing or other delays with log file analysis.
To help developers ensure their processor design meet the RISC-V specifications, Imperas has developed a directed test instruction generator and is now making many architectural validation test suites available.
The test suites cover over 3.5 million instructions for the RV32/64IMC ratified specifications, RISC-V Vectors, Crypto 0.8.0 draft specification and Bit Manipulation 0.93 draft specification.
Imperas provides Extendable Platform Kits (EPK) that are provided as source and include platform, models, scripts, and software to shorten the time to productivity. These include an example platform for use with Google RISCV-DV Instruction Stream Generator flow as well as a step-and-compare SystemVerilog encapsulation test bench and example platform for RISC-V functional coverage.
SystemVerilog supported platforms are available for use with Cadence Xcelium , Mentor Questa, Synopsys VCS environments and Metrics cloud-based solutions.
The riscvOVPsimPlus solution is an entry ramp for development and verification and includes a proprietary freeware license from Imperas, which covers free commercial use as well as academic use. The simulator package also includes a complete open-source model licensed under the Apache 2.0 license.
The free riscvOVPsimPlus package including the test suites and functional coverage analysis are now available on OVPworld at www.ovpworld.org
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