Fujitsu and Fraunhofer IIS join research efforts on nanometre chips
Fraunhofer IIS is complementing this with its own IP and decades of experience in IC and system design. Chip designs, right up to the GDSII data, are developed and evaluated together with customers. Fujitsu is producing prototypes in 90 nm and 65 nm CMOS technologies on multi-project wafers (MPW) at significantly reduced mask costs.
This means that the technology partners of Fujitsu and the IC developers at Fraunhofer IIS can implement fast and highly efficient solutions. There is potential for business models from prototypes (MPWs) via small series through to series production. “Industry, research and training all benefit from this co-operation. It grants cost-effective and dependable access to the latest nanometre technology for research projects, pilot series and products”, comments Josef Sauerer, Head of IC Design at Fraunhofer IIS.
Visit Fujitsu Semiconductor Europe at https://emea.fujitsu.com/semiconductor
Visit Fraunhofer Institute for Integrated Circuits (IIS) at www.iis.fraunhofer.de