As custom IC designs increase in complexity, engineers face the challenges of meeting stringent performance and reliability targets, especially at 28-nm and below manufacturing process nodes. Totem – a complete power noise and reliability platform for analog/mixed-signal chip designs – was selected by Fujitsu Semiconductor for its ability to handle large designs and analyze global noise coupling, which can impact chip performance and reliability. The software was also chosen for its integration with existing analog design tool environments, a feature that offers improved productivity.
"Apache’s Totem enables us to accurately model and simulate power/ground, substrate and package/PCB noise coupling at the full-chip level for advanced process technologies," said Masaru Ito, director of the technology development division, IP and technology development and manufacturing unit of Fujitsu Semiconductor Limited. "By using Totem, we can explore the impact of noise coupling on the circuit’s performance and determine if critical layout changes are needed early in the design process, allowing us to increase productivity and lower the risk of re-spin."
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