Fully integrated on-chip DC-DC converter tops 1.25GHz
Researchers in Switzerland have developed a fully integrated on-chip DC-DC converter topology that allows more than 20x higher switching frequency compared to existing integrated designs.
The converter developed at ETH Zurich and STMicroelectronics operates at 1.25GHz, which enables further scaling of the on-chip inductors and capacitors, achieving 0.21-1W/mm2 power density. Furthermore, the output power is delivered continuously by means of both magnetic and electric couplings, providing an output voltage ripple of under 1 percent without attaching any output capacitance.
Resonant switched capacitor (ReSC) DC-DC converter designs have needed 3D die-stacked inductors or PCB-integrated inductors to achieve appropriate power density values, posing challenges for monolithic integration.
The new design, shown at the ISCC conference yesterday, uses a voltage doubler built from two stacked class-D LC oscillators. The oscillators are coupled magnetically and electrically by on-chip transformers and flying capacitors, respectively. The single oscillator cell is implemented with two on-chip spiral inductors and an NMOS cross-coupled pair.
The oscillation frequency of 1.25GHz is determined by the inductance and the parasitic capacitance of the two NMOS transistors. The two oscillators are magnetically coupled by physically interleaving the inductors, while two flying capacitors provide electric coupling between the two oscillators. The electromagnetic coupling continuously delivers power to the output, which lowers the output voltage ripple and increases the power density. This allows the DC-DC converter desig can serve as either a voltage doubler or divider.
Two different versions of the DC-DC converter design were implemented in 180nm CMOS technology.
A high efficiency version used 7.8nH (coupled) on-chip transformers and a 458pF flying capacitor while occupying 1.61mm2. This had a 67 percent peak efficiency at 0.21W/mm2 while operating at 1.25 GHz switching frequency.
A high power density version occupies 0.37mm2 by adopting 3.1 nH (coupled) inductance and 152pF capacitance. This shows a much higher power density of 0.88W/mm2 but with a lower efficiency of 58.1 percent. The efficiency stays close to the peak efficiency from 70μW to 0.5W with less than 0.7 percent change, making the design suitable for various load conditions.
The researchers point out that 180nm CMOS does not provide a good balance of efficiency and high power density simultaneously due to the large parasitic capacitance of the switches and the low Q-factor of the transformers built with aluminium. Despite this, the technique enabled a high power density of 1W/mm2 .
The technique also scales to more advanced technology nodes with a smaller gate capacitance, positively impacting both the efficiency and power density.
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