Paper 10.5, 1Kbit FinFET Dielectric (FIND) RRAM in Pure 16nm FinFET CMOS Logic Process, written by Hsin Wei Pan et al. of Tsing Hua University in Taiwan but also attributed to multiple authors from foundry TSMC.
The organizers of the conference have released diagrams that show a little more of the structure and that the memory does not require a separate specialized device to contain the hafnium oxide non-volatile memory. Instead each memory cell is based on three fins with the high-k layer used as the memory element.
Schematic at left shows the cell structure of the device, along with a view showing that the corners of the FinFET were contoured to enhance the electric field. Source: IEDM.
The images in schematic and transmission electron microphotograph appear to show the unit cell composed of two FinFETs with one used as the selector switch. The second is connected to word line but what remains unclear is whether the memory switch is contained in one or both of these FinFETs.
Next: TEM photograph
The memory cell size is given as 265nm by 285nm, an area of 0.07632 square microns and comes with the particular benefit of not requiring any additional mask or process steps above that of the conventional logic process. The memory array is said to exhibit low-voltage operation, good retention and excellent reliability.
Side and top views of the ReRAM array architecture in the bitline direction, with a transmission electron microscope photograph of the actual structure between them. Source: IEDM.
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