Future chip architectures: inspired by factory concepts

Future chip architectures: inspired by factory concepts

Technology News |
Tomorrow’s embedded computing architectures will by far surpass those of today – in particular in terms of their complexity. Therefore, next-generation chips should be organized like agile factories, experts believe. A transatlantic research project is fathoming out future chip design principles.
By Christoph Hammerschmidt

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Researchers from the University of California, Irvine (UCI), the Technical University of Braunschweig and the Technical University of Munich have started a joint project to develop next-generation computer components for the new challenges of digitization. At the recent DATE 18 conference on electronics design and test in Dresden, researchers from these institutions introduced a joint project to devise a design methodology that would enable chipmakers to develop computer components ready to face the challenges that will come with the comprehensive digitization across all segments of economy – such as autonomous vehicles, advanced medical electronics or self-organizing production.  

Actually, the concept of the smart factory inspired the scientists: In today’s industry 4.0 shop floors, tool machines robots, sensors and computers are connected in many ways to form a complex cyber physical system. “To keep production running effectively and efficiently, factories need to properly manage logistics, supplies and facility controls to adapt to the current workload, while also considering maintenance and continuous operation,” said TU Braunschweig principal investigator Rolf Ernst, professor of computer and network architecture and deputy chairman of the Research Center for Digitalization, Informatics & Information Technology.


Future microelectronic systems face comparable requirements: While factories need to be provisioned with utilities, supply logistics and the like, the embedded computing infrastructure of the future requires similar logistics including thermal and power monitoring and control, clock control, various power supplies – and all these things not only to the chip as a whole but to various “chip islands”, explains Andreas Herkersdorf, professor and chair of integrated systems at the Munich Technical University (TU Munich). Examples of such chip islands are processing cores, I/O circuitry, application-specific accelerators, to name just a few – and they all have different needs.

Multi-Layer SO/SA stack

The similarities between the real-world factory and the complex chip architectures inspired the research team to name their concept “information processing factory.” This concept however does not only include just the semiconductor level (from semiconductor technology to processor architecture, but likewise the operating system and middleware. Their goal is establishing a range of self-organizing / self-aware (SOSA) entities at the various system levels. These entities are inter-related to collaboratively realize system-wide monitoring and control functions. Thus, complex SoCs will be able to constantly watch themselves and their operating parameters through embedded sensors, enabling to early detect performance degradation, thermal anomalies or other early indicators of a failure. Even certain security threats can be detected with this method, says Rold Ernst, professor of computer and network architecture and deputy chairman of the Research Center for Digitalization, Informatics & Information Technology. In case an imminent failure is detected, the concept provides for reserve resources, which can be activated if necessary.

Besides chip designs and computing architectures, the project also is designed to provide the design tools required to create such an information processing factory. In its current early microchip-focused phase, it is designed to be a pilot project by UCI and its German partners. Funding is provided by the National Science Foundation of the US and the German Research Foundation.

 

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