Gate drive design for enhancement-mode GaN FETs

Gate drive design for enhancement-mode GaN FETs

Technology News |
By eeNews Europe

In recent years, enhancement mode Gallium-Nitride (eGaNÒ) power transistors have emerged as promising next generation power switches for high power density switch mode power converters.  Significantly higher conversion efficiencies can be realized when compared with standard Si MOSFETs in a number of topologies such as Buck, Boost, Forward, and Flyback.  Given the same feature size, eGaN devices offer lower conduction resistance, smaller gate charge, and faster switching capability than comparable MOSFET devices.  Being configured as enhancement mode, allows eGaN devices to operate similar to power MOSFETs, minimizing the learning curve for power converter designers.  However, driving eGaN devices requires special considerations due to the low threshold voltage, fast switching speed and 6V gate-to-source maximum voltage rating.  Fortunately, newly optimized gate drivers are now available that solves the challenges of driving eGaN devices, enabling industry leading power density and efficiency while simplifying the task of driving eGaN FETs.

eGaN  Basics

The basis of Gallium Nitride’s performance advantages is that it uses a different conduction mechanism compared with silicon.  With silicon, electrons are bounded to atoms, and force is necessary to move an electron away from its atom.  With Gallium Nitride (GaN), a thin layer of aluminum gallium nitride (AlGaN) is applied to GaN forming a two dimensional electron gas (2DEG).  With a 2DEG, electrons are not bound to any atom, and are free to move with high conductivity and high velocity.  This results in a much smaller device for a given RDS(ON) and blocking voltage capability.  The basic structure is shown in Figure 1. 

Figure 1 – Basic eGaN FET Structure

A smaller device and a lateral gate structure yields a gate capacitance that is significantly lower than a comparable MOSFET.   The eGaN FET’s ultra-small package footprint and fast switching capabilities allow designers to push frequencies and power densities well beyond those practical with silicon MOSFETs.

Challenges of Driving eGaN Devices


Figure 2 – Transfer Characteristics of EPC2001    


Figure3 – Simplified Schematic of Turn-off Gate Drive Loop.

Low Gate to Source Threshold Voltage, VGS(TH)
eGaN FETs have a typical gate-to-source threshold voltage of 1.4 V which is low as compared with many MOSFETs used in power conversion, particularly higher voltage rated devices. Fortunately, eGaN FET’s  threshold is virtually flat with temperature.  Low threshold voltage does impact turn-off losses as there is only a small source voltage to drive the charge out of the gate during turn-off.  

As seen in the transfer characteristics curve in Figure2, switching action will take place when VGS in the active area of the structure is below 2 Volts.  During turn-off, a voltage is induced across any stray inductance, depicted as Ls in Figure 3, which is common to the gate drive and power loops. This voltage subtracts from the voltage driving current through the gate impedance.  The current commutation time associated with this effect is quantified in Equation 1 where LS is the inductance common to the gate drive and power loops, ID is the drain current, VDrive is the applied driver voltage, and VGS is the gate to source voltage at the active part of the structure.

t = LsID/ (VDRIVE-VGS)                                                    (1)

Any voltage ringing caused by Ls and the parasitic capacitors can result in unintended turn-on of eGaN FET, increasing losses and possibly even damaging the power converter.  To improve the gate drive noise immunity, it is critical to minimize stray inductance by layout optimization as well as minimizing the drive resistance.  The commonly used, gate resistor bypass diode shown in Figure 3, is not a solution and must be avoided. 

The LM5113, 100V, half-bridge gate driver overcomes the challenge of low threshold voltage in two ways.   This driver has separate sink and source outputs (as shown in Figure 5) allowing independent control of turn-on and turn-off without the harmful voltage drop of a bypass diode in the turn off direction.  This configuration is excellent for fast turn off and dv/dt immunity.  The LM5113 also has a very low sink impedance of 0.5 W for each driver.  

In addition, the eGaN FET structure has a very low ratio of QGD to QGS when compared with Si MOSFETs.  These eGaN FETs also have no external interconnects, such as wirebonds or clips or leads to contribute to common source inductance.  The PCB pattern for converters employing eGaN devices and optimized drivers can be laid out such that common source inductance can become very small, so even under the most extreme dv/dt conditions, the driver will hold the devices OFF. 

Figure 4 – RDS(ON) versus VGS of EPC2001

Figure 5 – Output Stage of LM5113


Maximum Gate-to-Source Voltage, VGS(Max)
eGaN FETs have an absolute maximum gate-to-source VGS(MAX) rating of 6 V, significantly lower than standard MOSFETs.  The challenge is that it takes about 4.5 V to fully enhance the eGaN FET, particularly at elevated temperatures as shown in Figure 4.  A voltage between 4.5V to 5.5V is a desirable safe gate-to-source voltage to realize minimum Rds(ON), and conduction losses.  The 4.5V to 5.5V window requires the gate drive bias supply be tightly regulated at about 5.0V.  There are two difficulties related to limited gate drive overhead.  During turn on, an under-damped circuit will cause overshoot on the gate that may exceed the absolute maximum rating.  This is solved with a gate drive incorporating separate pins for source and sink, as described earlier, allowing the tuning of turn on impedance without degrading turn off, as shown in Figure 5.  The second challenge involves high reverse conduction voltage during bootstrap charging which will be described in the next section.

Figure 6 – Bootstrap Circuit for High Side Drive


 Figure 7 – Reverse Conduction Characteristics of EPC2001


Figure 8 – Clamping Circuit for LM5113 High Side Driver

Reverse “diode” conduction voltage, VSD
A good ground referenced 5 V supply is available in many systems, and this supply is easily applied to the low side gate driver.

The most cost effective way to derive the supply for the floating high side gate drive is by using a bootstrap diode to charge the high side drive decoupling capacitor as shown in Figure 6.  When eGaN FETs are used as rectifiers and reverse current flows, the source to drain voltage is added to the floating boot-strap supply voltage.  An eGan FET reverse “diode” conduction voltage (source to drain voltage) varies with current, as shown in Figure 7. The bootstrap voltage will vary as it is dependent on the actual low-state switch-node voltage.  Although with minimal dead-time control this variation in the bootstrap voltage can be mitigated, it cannot be relied as a solution for a general application gate driver.  The gate to source voltage maximum limit of 6 V makes eliminating this variation necessary.  With no external gate limiter, the range of drive voltage can be greater than 2 V making it impossible to have both full enhancement and stay within the absolute maximum rating under all conditions.  The LM5113 gate driver overcomes this challenge by adding a proprietary clamp to the boot-strap circuitry as shown in Figure 8.  The clamp will limit charging of the bootstrap capacitor to 5.5 V, so full enhancement of the eGaN FET can be accomplished without overstressing the device’s gate.

A second challenge of high reverse conduction voltage is power dissipation due reverse current during dead-time (PDT).  This is particularly an issue as designers look to increase power density by pushing frequency higher.  Power dissipation is shown in equation 2 where f is frequency, VSD is reverse conduction voltage, iS is reverse conduction current, and tR is reverse conduction time for each transition. 

  PDT = 2fVSDiStR                    (2)

As frequency increases, PDT becomes a major contributor to overall losses.  The LM5113 has two means to reduce reverse conduction losses; (1) the propagation delays are matched typically within 2 ns and (2) the separate high side and low side inputs enable each input to be delayed and controlled separately.  These features, along with very low variation of delay times due to lack of common source inductance, enable much lower reverse conduction times than Si MOSFET based systems.

Ultra high dv/dt capability
eGaN FETs have extremely low Gate-to-Drain, or “Miller” capacitance (CGD), leading to very fast switching times.  Switching 48 V in less than 4 ns has been demonstrated.  In addition to keeping a device that is subjected to high dv/dt in the OFF state, the driver’s functionality must be immune to this same stress.  The LM5113 is capable of reliable operation at greater than 50 V/nS  – critical to managing losses as frequencies and power densities are increased.

Experimental Results

Figure 9 – Efficiency results of eGaN FET based board and MOSFET based board

Figure 10 – 1/8 Brick Converters, MOSFET Based (Top) and eGaN FET Based (Bottom)

The LM5113 has been demonstrated to unlock the efficiencies enabled by eGaN FET technology in both isolated and non isolated DC-DC converters, giving dramatic opportunities for component and board space reductions, or increased output power.   A fully isolated 1/8 brick was developed to convert wide input range 48 V (36 V to 75 V) to 12 V at 180 W and compared with a MOSFET based, 144 W output converter.  It should be noted that the eGaN FET based circuit runs at a 33% higher frequency.  Figure 9 compares the efficiency of the two, and presents some very noticeable differences.  The eGaN FET board’s efficiency rises very quickly to a high peak.  This is due to the low charge of the power devices and the driver’s ability to hold a device off to avoid shoot-through.  Most high efficiency circuits struggle at low power due to the high dynamic losses of MOSFETs.  Efficiency of the eGaN FET based system stays flat for most of its operating range.  This is due to, (a) a good balance of RDS(ON) and device capacitance, (b)the correct drive voltage, and (c) proper driver impedances. 

In Figure 10 it can be seen from the significant green space that the eGaN FET based design is much less densely populated, leaving room for even higher output power or board size reduction.

Figure 11 – Buck efficiency results

Figure 12 – Buck converter board

A 10 V, 10 A, eGaN Buck converter was also built.  The eGaN based design operates  at 800 KHz for inputs from 15 V to 60 V.   This eGaN design is compared with a Si MOSFET based, 100 W output Buck converter operating at 500KHz.  It should be noted that the eGaN FET based circuit runs at a 60% higher frequency.    Again, the rapid rise in efficiency at low load is very apparent in Figure 11 along with the large area of constant efficiency.  This indicates that the LM5113 driver is a very good match for the eGaN FETs, and there is much room for the board power to be increased.  Figure 12 shows this board and its very compact power stage.


If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles