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Generative AI provides 5x boost for RTL design

Generative AI provides 5x boost for RTL design

Business news |
By Nick Flaherty

Cette publication existe aussi en Français


Cadence Design Systems has developed an analysis and debug  tool to boost register transfer level (RTL) design and implementation productivity using generative AI.

Chip designers from ARM, Mediatek, Socionext and Alibaba’s T-head chip design unit are using generative AI in the Cadence Joules RTL Design Studio for fully optimized RTL design prior to implementation handoff.  This supports generative AI for RTL design exploration through the Cerebrus tool and big data analytics to provide physical estimates quickly and accurately. This can boost RTL design productivity by a factor of five and up to 25% quality of results (QoR) improvements in the RTL.

“Identifying RTL bottlenecks early in the design cycle is critical in IP development and enables quicker updates, higher quality RTL and improved PPA. For Arm specifically, Joules RTL Design Studio can help us identify problem points associated with congestion and deep logic, saving us significant time in finding the root cause, “said -Mark Galbraith, vice president of Productivity Engineering at ARM.

Joules RTL Design Studio expands upon Cadence’s existing Joules RTL Power tool by adding visibility into power, performance, area, and congestion (PPAC).

The intelligent RTL debugging assistant system provides early PPAC metrics as well as actionable debugging information throughout the design cycle—logical, physical, and production implementation—so engineers can explore “what-if” scenarios and potential resolutions to minimize iterations and improve design outcomes.
Joules RTL Design Studio shares the same engines as the Innovus Implementation System, Genus Synthesis Solution, and Joules RTL Power Solution, enabling users to access all analysis and design exploration features from a single GUI for optimal QoR.

Chip designers are increasingly using generative AI to boost productivity using Verilog.

The Cerebrus Intelligent Chip Explorer is used to explore design space scenarios, such as floorplan optimization and frequency versus voltage tradeoffs. This is linked to the Joint Enterprise Data and AI (JedAI) Platform allows trend and insight analysis across different versions of the RTL or across previous project generations.

Lint checker integration allows engineers to run lint checkers incrementally to rule out data and setup issues up-front, reducing errors and time to completion.

“Now RTL designers can rapidly access all the physical information needed for PPAC debug without having to wait for implementation, which previously took days or weeks,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence.

“Joules RTL Design Studio gives designers visibility into the challenges when they can still be addressed easily, ultimately speeding time to market. Our early engagements reaffirmed our initial target of up to 5X faster RTL convergence and up to 25% improved QoR.”

Chip designers using generative AI 

“Our engineers were able to achieve 2-3X better productivity through analysis efficiency, significantly reducing iterations between RTL designers and implementation,” said Shunji Katsuki, general manager, SoC System Development Division, Global Development Group at Socionext.

“Joules RTL Design Studio provides us with a robust and efficient mechanism to find and categorize timing violations based on logical and physical causes as well as bottleneck analysis and cross-probing to RTL, schematic, and layout. Design issues were discovered earlier than they would have been with our previous front-end design process. In conjunction with the complete Cadence digital full flow—Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution—our design schedules were further reduced. In addition to the design we’re working on currently, we plan to use Joules RTL Design Studio to improve design efficiency with future projects.”

“Our RTL design teams focus on creating silicon products that deliver smarter user experiences with more performance and power efficiency. This requires making design decisions based on early estimates of power, performance, area, and congestion,” said Harrison Hsieh, senior general manager of Silicon Product Development at MediaTek.

“Joules RTL Design Studio’s accurate physical prototyping allows our designers to innovate with confidence, reducing the number of iterations between front- and back-end teams, allowing MediaTek to get its wide variety of differentiated products to market faster.”

“With Joules RTL Design Studio from Cadence we can achieve efficient and accurate power breakdown analysis much earlier in the design phase. The tool’s power prediction capability allows quick RTL optimization iterations so our design team can speed RTL optimization effectively,” said Zejian CAI, COT Methodology, T-Head, Alibaba.

 www.cadence.com/go/joulesrtldspr.

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