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Gowin aims 22nm FPGAs at the high-end

New Products |
By Peter Clarke


The Arora V FPGA family, manufactured using 22nm SRAM technology, is available from Gowin Semiconductor Corp. (Guangzhou, China).

FPGAs come with 270Mbps-12.5Gbps high speed serdes interfaces, PCIe 2.1 hard core with support for PCIe x1, x2, x8 modes, along with MIPI hard core single lane module at up to 2.5Gbps, and DDR3 interfacing at speeds up to 1333 Mbps.

The first family device, the GW5AT-138FC676, features 138K LUT logic resources, 6.4Mbytes of block RAM, 1.1Mbytes of distributed SRAM, along with advanced DSP blocks, and an integrated ADC. Future family devices include 25K (non-Serdes) and 60K LUT devices.

Arora V integrates many hardwired modules as well as soft IP solutions for various interfaces such as PCIe 2.1, MIPI DSI, DDR3, SGMII, XAUI, Gbe, SDI and USB3.1.

“Having entered and now proliferated in the low and mid density FPGA market space, this family further enhances our leadership position and is based on genuine innovation with advanced development,” said Jason Zhu, CEO, of Gowin.

Rival

Gowin has a Chinese rival seeking to address the high-end of the market. Suzhou Yige Technology Co. Ltd. (Suzhou, China) – founded in January 2022 and otherwise known as EagleChip – has raised 286 million yuan (about US$41.5 million) in an “angel” round of funding (see Chinese FPGA startup raises first funds).

“The Arora V family integrates many innovative hard core modules that have been developed internally by Gowin, including fully controllable high-speed serdes ideal for supporting applications requiring very high data rates such as communication, video aggregation, and AI computing acceleration. New architecture DSP modules, block RAM modules supporting ECC error correction, high performance multiple voltage GPIO, and high accuracy clock architecture are all featured in Arora V,” said TP Wang, CTO of Gowin.

Related links and articles:

www.gowinsemi.com

News articles:

Chinese FPGA startup raises first funds

Gowin offers ARM-based FPGA-SoC

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