Gowin Semiconductor Corp. (Guangzhou, China) has filled out its Arora-V FPGA family with smaller LUT device offerings.
When the family was launched in September 2023, based on 22nm SRAM technology, it was with the GW5AT-138FC676 that featured 138K LUT logic resources, 6.4Mbytes of block RAM, 1.1Mbytes of distributed SRAM, along with advanced DSP blocks, an integrated ADC and a hardened RISC-V processor core (see Gowin aims 22nm FPGAs at the high-end).
The extended family now includes 15K, 45K, 60K, and 75K LUT device offerings. The latest offering includes 12.5Gbps high-speed SerDes interfaces, PCIe hardcore, MIPI hardcore D-phy and C-phy support, RISC-V microprocessor, and DDR3 interfaces.
The Arora-V programming configuration provides designers with options including JTAG, SSPI, MSPI, CPU, and the ability to directly program external SPI Flash in JTAG or SSPI Mode. In addition, it allows for indirect programming of external Flash in other modes using a soft-core IP bridge and supports background upgrades, bitstream file encryption, and security bit settings.
Gowin also claims Arora V has superior Single Event Upset (SEU) resiliency compared to competitors’ FPGAs. Gowin provides an SEU Handler in the form of wrapper IP that allows users to access SEU reports and correction functions.