Gowin heads into automotive, 12nm FPGA
FPGA ‘startup’ Gowin Semiconductor is expecting to receive ISO26262 certification for its FPGAs for use in automotive as it prepares a 12nm FinFET device and looks at chiplets for AI accelerators.
The certification from TÜV Rheinland expected this week is a key step for the company, CEO Jason Zhu tells eeNews Europe. “It’s tough for a startup and today we have shipped 100m units in the last ten years,” he said.
“One thing that is a great opportunity for FPGA is automotive,” he said. “Five years ago people started looking for the next big market and looked at making the car smarter especially in China. Replacing the engine and transmission with motors and that’s what they have been doing for years.”
“But the market is very fragmented and that’s a golden opportunity for FPGA and they need automotive grade which makes the ASIC approach more difficult and that makes it the right time. We have had a lot of parts qualified to AECQ100 and now we expect TUV ISO26262 certification,” he said.
- Gowin fills out Arora-V FPGA family
- First 22nm FGPA with hardened RISC-V cores
- 22nm FPGAs aim at the high-end in Europe
The world’s largest electric car maker BYD is the company’s biggest customer in China for an IGBT driver and we it supplies Toyota’s joint venture in China as well as for a head up display system.
“So we can help customers in Europe and the US catch up with China.”
The company has three families, ranging from the high end Aurora 5 family built on the TSMC 22nm process with high speed serial interfaces and a hard wired ARM Cortex-M3 controller core running at 200MHz as well as a version with a RISC-V core.
Then there is the Arora 2 SRAM-based FPGA built on TSMC’s 55nm and the LittleBee flash-based non-volatile FPGA. “All can be AECQ100 qualified,” he said.
The next step is to larger devices for industrial applications and AI.
“If you look at the cost curve 28 and 22nm is the sweet spot, the next node is 16nm and that’s FinFET which is more expensive. We have the Arora 7 family in the pipeline on a 12nm FinFET process with 400K LUTs (look up tables) but that is a big device for other markets with DSP for 5G/6G, medical, ASIC emulation. We are not looking to replace the main processor, we will be sitting next to them for the interface,” he said.
“We are looking at our customers, to see who is using AI and they are developing their own technologies and we will work with academics,” he said. “A CPU plus and FPGA is not enough to dethrone Nvidia but if you do something in the FPGA architecture there is an opportunity. We are in the stage of finding out the balance of accelerators and fabric. We have simple SiP with a hardwired M3 MCU or SRAM for cost but we are looking at chiplets.”
He points to a an EV battery supplier that is using an industrial vision inspection system to monitor the quality of the materials on the production line. A traditional vision system has 83% accuracy, and using convolutional neural networks (CNN) AI with industrial PC increases this to 98% but the image resolution is only 10m/min.
“With our FPGA we can divide the image into 8 and use the PCI Express interface to the PC to give 100m/min,” he said.
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