UK AI chip designer Graphcore has joined a European project to create a supercomputing framework for emerging AI applications in the real world.
The €2.6m three-year SparCity project will focus specifically on sparse AI, where there is not much correlation in the data. The tools developed during the project will be used to demonstrate the effectiveness of the framework in four real-world areas: computational cardiology, social networks, bioinformatics and autonomous driving.
SparCity is part of the broader EuroHPC Joint Undertaking (JU) launched in 2018 to increase Europe’s competitiveness in high-performance computing through the development of multiple exascale supercomputers.
Graphcore was one of the original proposers of the project, alongside Sabanci Universitesi in Turkey, Simula Research Laboratory in Norway, INESC-ID in Portugal and Ludwig-Maximilians-Universitaet Muenchen in Germany, with the coordination of Koç University (Turkey).
Much of the compute capacity used to run AI models is spent performing mathematical operations on parameters that are not relevant to the problem being addressed because meaningful parameters are sparsely distributed across the same models.
The inefficiency of spending time and energy processing valueless data is being compounded by the exponential growth in size and complexity of AI models.
Sparse computation involves new techniques that focus processing power on those elements of a model that are most relevant to solving a specific task. Graphcore’s IPU chip and software technology is specifically designed for AI compute and includes characteristics such as the ability to execute many, very different calculations independently and in parallel, which are essential for sparse computations. This can reduce the power consumption but needed new hardware and software. Bristol-based GraphCore has raised $710m for the development, valuing the company at over $2bn and making it the best funded AI chip startup in the world.
Sparsity is also supported at a software level with sparse kernels and libraries. These will be used and further developed during this project, along with performance and energy modelling, with the resulting models used to drive optimisations. Considerations will include the design choices underpinning data storage and movement, precision, and kernel implementations.
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