Growth in mobile data traffic focuses NXP technology on the wireless infrastructure sector

Growth in mobile data traffic focuses NXP technology on the wireless infrastructure sector

Interviews |
By eeNews Europe

In recent weeks NXP Semiconductors has revealed two major developments that are targeting the burgeoning wireless infrastructure sector.    

Earlier in May the company unveiled a new 16-bit dual-channel LVDS DDR interface Digital-to-Analog Converter that supports output update rates of up to 1.25 Gsps. The high-speed DAC claims to offer the best-in-class single tone SFDR performance and two-tone intermodulation distortion across a broad output bandwidth of 200 MHz.    

Developed primarily for wireless infrastructure applications, the DAC1627D1G25 is fully compliant to the Multi-Carrier GSM spectral mask and the LTE and LTE-Advanced transmit specification, with comfortable margins.  As a result, the DAC1627D is ideal for multi-standard radio base stations, allowing design engineers to employ a single DAC transmit architecture thereby minimizing the system bill-of-material costs.         

During the last few days of April NXP also unveiled CGVxpress, which is an extension to its high speed data converter technology portfolio and the next generation of the CGV high speed serial interface announced in 2009. The new interface will be used in future NXP ADC and DAC product families.    

The CGVxpress feature set also includes support for Multi-Device Synchronization (MDS). MDS solves tough system synchronization and latency challenges in many digital communications system applications, including LTE and LTE-Advanced MIMO radio base stations.    

eeNews Europe:  Where have you developed the new DAC and the CGVxpress technology?

Wood:  NXP has a pretty big R&D site in Caen in Northern France where we do our high-speed ADC development and in Eindhoven we have our high-speed DAC development so we can claim six decades of mixed-signal technology experience.

eeNews Europe:  What applications is NXP targeting with the release of the DAC1627D1G25 DAC? 

Wood:  We are mostly focused on base stations because base stations have the lion’s share of high-speed data conversion market for both ADCs and DACs. 

The opportunity for this new DAC is focused on base stations and wireless infrastructure that is associated with the dramatic growth in mobile data traffic.  We are currently seeing around 0.6 exabytes per month of global mobile data traffic which is estimated to go up to 6.3 exabytes per month by 2015.  What is driving that growth is mostly video with internet access, M2M connections as well as gaming and VOIP.  There is a lot of growth in mobile data traffic which is driving a need for base stations.      

We get asked a lot about femtocells and whether they will bite into the need for macro and pico cell basestations.  The answer is it does eat into that a bit but not very much.  About 800 million terabytes per month of mobile data traffic will be go over to femto cell base stations but that still leaves about 6.3 exabytes of data per month by 2015 across the more traditional macro, pico and micro cell base stations.    

The volumes of traditional macro and micro base stations that you tend to see on towers along the side of the road will flatten out to about a million units towards the end of 2014 and going into 2015.  The majority of shipments in that timeframe will be small cell base stations like pico or micro.  The good news for us is that the new converters we are developing will be used in macro, micro and pico base stations. They will not be used in femto applications.    

A good example of this trend to small cell base stations is the Alcatel-Lucent lightRadio or the active antenna array.  The cubes use arrays of either 1 x8 or 8 x 8 and they use beam-forming or beam-steering to maximize the efficiency of small base stations.  They are really intended for rural areas or urban environments with a low density of users.    

The small form factor of the device really relates directly to the serial interface we are planning to introduce later this year.  That is CGVxpress, which really allows companies like Alcatel-Lucent to create innovative form factors for these small cell base stations.
eeNews Europe:  What do you see as a key benefit of the new DAC1627D1G25 DAC?

Wood:  The 1G25 is reference to the fact that we can update the output at a rate of 1.25 Gsps.  We can accept incoming data at 312.5 Msps and interpolate that up to a maximum of 1.25 Gsps but perhaps the most important point is that we are fully compliant to the very challenging Multi-Carrier GSM spectral mask which requires a combination of high linearity, low noise and high dynamic range.  We also comply with LTE/LTE-A Tx specifications by a comfortable margin.  

It is something we have worked hard to get to through a number of different circuit innovations including a very low noise DSP implementation and innovative capacitor current source calibration that is done on device start-up.  We have also introduced a new feature with Multi-Device Synchronization (MDS) which also relates to the CGVxpress announcement and this is two hardware pins on the DAC that if they are used will allow the designer to align the analog outputs of up to 16 DAC outputs (that would be eight of these dual-DAC devices for example).  That is important for MIMO transmitters where you really need to have perfectly coherent outputs going to the transmitters in order for the spatial multiplexing algorithm to work.    

eeNews Europe:  What are the major performance benefits for the new DAC? 

Wood:  Almost all base stations, be they macro, micro or pico, now all use Digital Pre-Distortion (DPD) to linearize the RF power amplifier because it is the PA that consumes the majority of the power in the base station. Typically those RF PAs are not very linear. So by using Pre-Distortion, in which you essentially send the inverse transfer function of the PA, you are able to pre-distort the transmit signal with that characteristic to enable you to get 10 or 20 percent more efficiency from that power amplifier and really increase the energy efficiency used. 

The challenge is that when you are examing the output of the RF PA it goes through a demodulator and some ADCs so you will want to look at the fifth, seventh or even ninth harmonic distortion of the PA to try and account for those.  So you will need plenty of bandwidth. 

For example, LTE uses a 20 MHz modulation band.  You need to have at the 7th order 140 MHz to properly linearize the PA.  The good news is that this new DAC has 270 MHz of input data bandwidth.   So there is plenty of bandwidth even for two channels of LTE/LTE-A with DPD applied to it.      

We also show the highest mixed-signal performance over extended data bandwidth.  We are showing DC from about 250 MHz bandwidth from 10 dB to about 5 dB higher SFDR range compared with our nearest competitor.  That performance is maintained for both zero-IF and high-IF. 

The chip does have interpolation as well as a digital modulator and numerically controlled oscillator so you can frequency shift the output prior to conversion to analog.  So an ideal use of this part would be a 200 MHz input signal which might be a 40 MHz 2 LTE bands with a DPD listening at five times that for digital pre-distortion so up to 200 MHz and that covers you for single multi-carrier narrowband and wideband which accommodates 2G all the way to 4G embracing GSM, GPRS, EDGE, MC GSM, W-CDMA, LTE and LTE-A.

eeNews Europe:  How have you achieved the level of MC GSM spectral mask performance?

Wood:  The AD9122 was previously considered to be the state-of-the-art high speed but we now believe the DAC1627D defines the new reference standard for state-of-the-art high speed DACs at equivalent power consumption.    

On the issue of the MC GSM spectral mask our noise floor and spurs are well outside the spectral mask.    

We have reduced the noise coupling into the analog through the implementation of a DSP engine that is very low noise. It uses a 16-phase clock instead of a typical two-phase clock.  Capacitors are used as a current source for the DAC and they ordinarily CMOS capacitors are very non-linear across a die.  The value of those capacitors is quite broad and so we have developed a method of calibrating those capacitors so that those current sources they are very linear. Those are the two main contributions to the high performance.      

Typical dynamic performance figures include the following:

SFDR = 85 dBc (FOUT=150 MHz, FS= 1.25 Gsps, BW = 180 MHz)

NSD (FOUT= 20 MHz) = -161 dBm / Hz

NSD (FOUT= 153 MHz) = -158 dBm / Hz

IMD3 (FOUT= 150 MHz, DF= 3 MHz) = 82 dBc 

The SFDR is a classical measure of high-speed data converter performance.  

With the AD9122 our analysis shows it has a spur on the third or fourth order harmonic of the fundamental.  It is about 68 dBc below full scale whereas with the DAC1627D under the exact same test conditions the highest spur is the second harmonic and is on 87 dBc below full scale so there is considerably higher linearity as measured by SFDR.  This is the kind of thing that an instrumentation engineer, somebody who is not doing base station design, is going to look at very carefully. SFDR is going to be a clear indication of the purity of the output spectrum.

eeNews Europe:  Do you have demo board available yet?    

Wood:  We do have a demo board and we are out with customers right now doing demonstrations.   

Figure 1: DAC1627D Demo board block diagram

The board has a connector CGAP2 connector (shown on the left) that is our signal generator board that is available to our customers.  They can plug into the memory of that board whatever test waveform they want to look at.   We have different sources of clocking for the DAC clock and also for the LVDS clock and there is also a chip that converts USB to SPI.  We have a SPI bus that controls the configuration of the DAC and we also supply PC software so the customers can just plug a USB into the board to allow them to control and configure the DAC for their particular operating point.    

We will have a high-speed serial interface version of the demo board within the next few months but currently it is the more traditional parallel LVDS DDR interface.  Of course when you use that parallel interface you need to make sure that each one of the wires is the exact same length so that you can de-skew that bus to ensure the clock and data arrive at the same time.

eeNews Europe:  Is the DAC1627D1G25 available now and when will it go into production? 

Wood:  The DAC1627D1G25 is available now and is likely to go into production in three or four months following the typical characterization cycle and going through all the life testing checks.

eeNews Europe:  What type of interface are you using with the DAC1627D1G25 DAC?

Wood:  The DAC1627D1G25 is a high-speed 16-bit, dual-channel radio frequency DAC which uses a LVDS DDR digital parallel interface.  We will have over the next few months a CGVxpress version of this device which uses the serial interface which allows us to put it into a smaller package.  When combined with CGVxpress and CGV, NXP’s implementation of the industry-leading JESD204A high speed serial interface, NXP has a roadmap that meets the most demanding digital radio transmitter signal fidelity requirements.

eeNews Europe:  What is the significance of the recent CGVxpress announcement?

Wood:  Why are we doing CGVxpress?  Well NXP Semiconductors is a world leader in high-speed interface products.  We have been working on high-speed converters for a number of years mostly embedded into ASICs but now into standard products.  It is sort of natural that we should lead the transition to high-speed serial interfaces for data converters.  We feel this is inevitable.  It is equivalent to the transition to USB, SATA, Gigabit Ethernet, PCI Express.  All these are high-speed serial interfaces now.       

NXP is continuing to strengthen its leadership position in high-speed serial interfaces with a major enhancement to CGV, and set the pace for data converter innovation.  CGVxpress is the new high-speed serial interface specifically for high-speed converters and extends NXP’s SERDES-based high speed converter interface leadership.     

CGVxpress delivers value that goes beyond traditional parallel interfaces, providing dramatic enhancements to ease-of-use, cost benefits and system architecture. The technology and performance enhancements enabled by CGVxpress will drive this serial interface into ubiquitous adoption by data acquisition system engineers worldwide.    

CGV is NXP’s implementation of the JEDEC JESD204A interface standard, which appears on numerous high speed ADC (including the ADC1413D) and DAC (including the DAC1408D) product models.  What we have done with CGV is to work very hard with our partners Altera, Lattice and Xilinx to ensure we interoperate with their logic devices.  They all have SERDES-based FPGAs and there is some digital logic that needs to support the SERDES and we have been working with them to make sure that their implementations of their logic are compatible with CGV and CGVxpress transmitters and receivers. We will be demonstrating CGVxpress publically at theIEEE International Microwave Symposium (MTT-S) to be held in early June 2011 in Baltimore, Maryland, USA.  The demonstration will show a 4.5 Gbps CGVxpress transmitter over a 20 cm differential lane reach.

Multi-Device Synchronization (MDS) which solves tough system synchronization latency engineering issues at the board level have been built in to be a feature of CGVxpress.  Both on the ADC transmitter and the DAC receiver part of the interface.      

Our CGV boards were based on Xilinx and we subsequently have made a bit of a shift towards Altera but we have boards today from all three vendors.      

With CGVxpress you can separate by at least 20 cm the distanced between the sensitive mixed-signal data converter versus the high-speed digital, noisy FPGA or ASIC or microprocessor.  There is lots of good isolation you can get there.      

There is an adoption cost in the sense that your design and test engineers have to be familiar with this but the BOM cost savings will quickly exceed the adoption costs.  It is really a slam dunk from an engineering management perspective.     

All the channel synchronization, scrambling and error detection are all built into state machines.  There is no software that is needed to be loaded.  It is plug-and-play solution.      

The board size can be reduced (by up to 10%) because the package count is lower because there are fewer pins.  The system reliability is enhanced (by up to 10%) because there are fewer points of interconnect.  The board cost is reduced (by up to 25%) because you can eliminate routing layers and it is much simpler to route.  The PCB design effort costs are less (by up to 20%). 

The BOM cost is reduced because you do not have to worry about external logic for doing the synchronization which is critical in communications systems.  Then you can change the resolution if you need to of your converter because our pin-out typically does not change from 14-bit to 16-bit as it is an abstracted serial interface now.  There is no one-to-one connection now for the number of wires with the number of bits.  So with just a simple FPGA change you can change your converter resolution if necessary.

eeNews Europe:  What do you see as being the key application areas for CGVxpress?

Wood:  CGVxpress is ideal for wireless infrastructure (WIFR), industrial, scientific, medical (ISM), and aerospace and defense (A&D) applications, where high bandwidth, sample accurate lane synchronization and deterministic latency are critically technical requirements.    

CGVxpress has error correction and it has scrambling.  It has all these very sophisticated features that other interfaces do not offer.  The wire length does not matter because there are FIFOs built-in to the transmitter and in to the receiver.      

We provide the transmit and receive IP on the DAC and there is also IP that is required to be connected up to the SERDES on their FPGA.  There is a single so-called sideband signal called SYNC which is just a way for the receiver to indicate to the transmitter that it has not been synchronized.  There are some protocol steps that are taken, some sequencing steps initially and once you are done with that you are just transmitting data.  It is very low overhead and very high bandwidth.

eeNews Europe:  Are there any additional benefits of CGVxpress?

Wood:  CGVxpress dramatically reduces the number of interconnect signals between the data converters and logic devices.  It also solves a major base station system design challenge by synchronously bonding multiple data lanes with sample level accuracy.    

A further benefit of CGVxpress is that it facilitates significantly reduced PCB design and manufacturing complexity, impacting both NRE costs and marginal production costs.  Systems can often be implemented using fewer PCB layers compared with traditional parallel interfaces.

NXP unveils CGVxpress High Speed Serial Interface
World’s highest performance RF DAC enables linearity performance breakthroughs

More information about NXP’s CGVxpress technology at:     

More information on the DAC1627D1G25 digital-to-analog converter at    

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