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GUC delivers first 3nm, 5nm chips using AI tool

Business news |
By Nick Flaherty


Taiwanese design house Global Unichip Corp (GUC) has successfully delivered its first design on TSMC’s 3nm N3 process as well as a 5nm CPU that used a machine learning design tool from Cadence Design Systems

The 3nm high performance computing chip design was created using the Cadence Innovus Implementation System with 3.5 million instances that reached clock speeds of up to 3.16GHz.

The CPU design was created using the AI-enabled Cadence Cerebrus Intelligent Chip Explorer and the digital full flow on the TSMC N5 process technology, reducing the power by 8% and the size by 9%. Cerebrus uses reinforcement learning engine that autonomously optimized GUC’s design flow, allowing the team to exceed human engineering potential and accelerate time to market.

The GigaPlace engine in the Innovus Implementation System tool provided GUC with support for TSMC FINFLEX cell row placement and consideration for pin access throughout the flow for N3 design rule checking (DRC) closure.

The GigaOpt engine delivered improved optimization by enabling the most optimal configuration from the TSMC N3 library while balancing different cell row utilization. The Innovus Implementation System also includes a massively parallel architecture and incorporates the well-established NanoRoute engine, which enabled GUC to address signal integrity early in the design flow while improving post-route correlation.

“GUC is a market leader providing advanced chip solutions for AI, HPC, 5G, industrial and other emerging applications,” said Dr. Louis Lin, senior vice president of Design Services at GUC.

“Given our commitment to deliver the most competitive designs to our customers, it is important for us to invest in leading-edge technologies. The Cadence Cerebrus Intelligent Chip Explorer, in conjunction with the broader digital flow, was the natural choice to help us achieve faster design turnaround via AI technology while also improving PPA,” he said. 

“The Innovus Implementation System was instrumental in helping us deliver our first N3 chip, enabling our team to accelerate the creation of our high-performance, low-power HPC design.”

www.cadence.com


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