Hardware debugger for the fastest (IP) 8051 & 80251
The system is called DoCD (DCD’s on-Chip Debugger) and consists of the Debug IP Core, Hardware Assisted Debugger and Debug Software. It features instruction smart trace buffer (configurable up to 8192 levels), hardware debugging, software simulation and verification. DoCD provides some features such as a real-time and non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on-chip software debugging. It allows hardware breakpoints, trace, variables watch and multi C sources debugging. “DoCD Debug software can work as a hardware debugger, as well as a software simulato,” explains Tomasz Krzyzak, vice-president at Digital Core Design, “some tasks can be validated at software simulation level and after this step, it can continue real-time debugging by uploading code into silicon.”
The DoCD user can use their favourite C compilers or assemblers for software development – it supports most of High Level Object files produced by C/ASM compiler tools:
Extended OMF-51 produced by Keil compiler
IAR EWB 8051 & 80390 workbench
OMF-51 produced by Tasking compiler
Standard OMF-51 produced by some 8051 compilers
Extended OMF-251 produced by Keil compiler
NOI format file produced by SDCC-51 compiler
Intel HEX-51 format produced by each 8051 compiler
Intel HEX-386 format produced by each 80390 & 80251 compiler
BIN format produced by each 8051 & 80390 & 80251 compiler
System-on-Chip designs are facing, says DCD, a problem of inaccessibility of important control and bus signals, because they often lie behind the physical pins of the device – that makes traditional measurement instrumentation useless.
TheDoCD Hardware Debugger provides debugging capability for a whole System-on-Chip (SoC); non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method not only saves time, but also benefits the size of the IST buffer and extends the trace history. Captured instructions are read back by the DoCD-debug software, analysed and then presented to the user as an ASM code and related C lines.
The system consists of three major blocks:
– Debug IP Core, a real-time hardware debugger, which provides a access to all chip registers, memories and peripherals, connected to DCD’s IP Core (Dx8051/DQ80251/Dx80390). It controls CPU work, by non-intrusive method. The Debug IP Core is provided as Verilog or VHDL source code, as well as FPGA netlist – depending on the customer requirements.
– Debugger Software – DoCD Software (DS) is a Windows based application. It is fully compatible with all existing 8051/80251/80390 C compilers and Assemblers. The DS was designed to work in two major modes: software simulator mode and hardware debugger mode. Those two modes, allow the pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon – using debugger mode.
– Hardware Assisted Debugger – a high-performance Hardware Assisted Debugger is connected to the target system, containing the DCD’s core, either in FPGA or ASIC. HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (JTAG/TTAG/DTAG protocols) inside silicon and a USB port of the host PC, running DoCDTM Debug Software.
DCD; https://dcd.pl/page/154/docd/
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