HBM3 memory subsystem advances AI/ML performance
The solution supports data rates of up to 8.4 Gbps and can deliver over a terabyte per second of bandwidth – more than double that of high-end HBM2E memory subsystems. With a market-leading position in HBM2/2E memory interface deployments, says the company, it is ideally suited to enable customers’ implementations of accelerators using next-generation HBM3 memory.
“The memory bandwidth requirements of AI/ML training are insatiable with leading-edge training models now surpassing billions of parameters,” says Soo Kyoum Kim, associate vice president, Memory Semiconductors at IDC. “The Rambus HBM3-ready memory subsystem raises the bar for performance enabling state-of-the-art AI/ML and HPC applications.”
The company says it achieves HBM3 operation of up to 8.4 Gbps by leveraging over 30 years of high-speed signaling expertise, and a strong history of 2.5D memory system architecture design and enablement. In addition to the fully-integrated HBM3-ready memory subsystem, the company offers interposer and package reference designs to speed their products to market.
Benefits of the company’s HBM3-ready memory interface subsystem are offered as the following:
- Supports up to 8.4 Gbps data rate delivering bandwidth of 1.075 Terabytes per second (TB/s)
- Reduces ASIC design complexity and speeds time to market with fully-integrated PHY and digital controller
- Delivers full bandwidth performance across all data traffic scenarios
- Supports HBM3 RAS features
- Includes built-in hardware-level performance activity monitor
- Provides access to Rambus system and SI/PI experts helping ASIC designers to ensure maximum signal and power integrity for devices and systems
- Includes 2.5D package and interposer reference design as part of IP license
- Features LabStation development environment that enables quick system bring-up, characterization and debug
- Enables the highest performance in applications including state-of-the-art AI/ML training and high-performance computing (HPC) systems
Matt Jones, general manager of Interface IP at Rambus says, “With the performance achieved by our HBM3-ready memory subsystem, designers can deliver the bandwidth needed by the most demanding designs. Our fully-integrated PHY and digital controller solution builds on our broad installed base of HBM2 customer deployments and is backed by a full suite of support services to ensure first-time right implementations for mission-critical AI/ML designs.”
See more on the Rambus HBM3 controller and HBM3 PHY.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
