HBM4 standard doubles channel count for AI boost
JEDEC Solid State Technology Association has published its standard for HMB4 high speed memory, doubling the channel count from 16 to 32 for higher performance.
The JESD270-4 HBM4 brings higher bandwidth and larger stacks of higher capacity DRAM memory die to AI chips in particular.
With transfer speeds up to 8 Gb/s across a 2048-bit interface, HBM4 boosts total bandwidth up to 2 TB/s with two pseudo-channels per channel. This provides designers with more flexibility and independent ways to access the 4-high, 8-high, 12-high and 16-high stack of DRAM die. These can have densities of 24 Gbit or 32 Gbit, providing for a higher cube density of 64GB.
The standard supports vendor specific voltage levels for the data output buffers (VDDQ) at 0.7V, 0.75V, 0.8V or 0.9V and the VDDC core at 1.0V or 1.05V for lower power consumption and improved energy efficiency.
“The introduction of HBM4 marks a critical step forward in high-bandwidth memory innovation, delivering the performance, efficiency, and scalability required to power the next generation of AI, HPC, and graphics workloads,” said Joe Macri, Senior Vice President, Corporate Fellow and Compute and Graphics CTO at processor designer AMD.
The HBM4 interface definition ensures backwards compatibility with existing HBM3 controllers, allowing for seamless integration and flexibility in various applications and allowing a single controller to work with both HBM3 and HBM4 if needed.
The standard also adds Directed Refresh Management (DRFM) for improved row-hammer mitigation and Reliability, Availability, and Serviceability (RAS).
“The tremendous growth in AI model sizes demands higher memory bandwidth to improve the efficiency of AI hardware systems with heterogeneous compute architectures, ensuring rapid and seamless data movement at a large scale. The HBM4 standard addresses this need for higher bandwidth with significant enhancements,” said Boyd Phelps, Senior Vice President and General Manager of the Silicon Solutions Group at Cadence Design Systems, which is buying the Artisan foundational IP business from ARM to add to its memory IP.
“The rapid adoption of multi-die designs for HPC and AI applications, requiring significant compute performance, is driving new innovations in HBM technologies,” said Neeraj Paliwal, SVP of Product Management at EDA tool vendor and IP provider Synopsys. “As an active member of JEDEC, Synopsys is driving the development and adoption of the HBM4 standard, which companies can leverage to meet the memory capacity and performance targets of their multi-die designs with a complete HBM4 IP solution that has been adopted by multiple customers.”
“Micron played a pivotal role in the development of the HBM4 JEDEC standard, working closely with industry leaders and ecosystem collaborators to drive innovation and set new benchmarks in memory technology,” said Praveen Vaidyanathan, Micron Vice President and General Manager of Data Centre Business.
“Samsung has been at the forefront of the HBM technology and market growth through supporting technical advancements as well as close collaborations with industry stakeholders. As part of this initiative, Samsung is pleased to have taken part in the HBM4 JEDEC standardization work over the past three years,” said JS Choi, Corporate Vice President and Head of Memory Biz Product Planning Team. “Samsung looks forward to bringing high-performing products to market that leverage the enhanced memory bandwidth, capacity, energy efficiency and other key performance attributes of the HBM4 standard.”
“In the rapidly evolving landscape of technology, artificial intelligence (AI) is advancing and spreading at an unprecedented pace, outpacing many other applications in history. High Bandwidth Memory (HBM) stands as one of the crucial components driving AI performance. Through the adoption of the HBM4 JEDEC Standard, this technology promises to deliver even higher bandwidth and the best power efficiency available,” said Jeff Choi, VP, HBM Business Planning, SK hynix
To download JESD270-4, visit the JEDEC website.
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