HC11 re-coded in silicon IP – 4 times faster architecture
The DF6811E is a redefined 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. Even though it is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller, DCD’s IP Core has an improved FAST architecture, approximately four times faster when compared to the original implementation. In the standard configuration, the core has integrated on-chip, major peripheral functions in one of the following configurations:
68HC11A/68HC11D/68HC11E.
The D6811E implements two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. The Core offers also enhanced security by implementing self-monitoring circuitry included on-chip and the Computer Operating Properly (COP) watchdog system to protect against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if an illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power.
The DF6811E Microcontroller Core can be equipped with the ADC Controller, which allows use of an external ADC Controller with standard ADC software. The ADC Controller makes external ADCs visible as internal ADCs in the original 68HC11E Microcontrollers. The DF6811E has a built-in real time, on-chip hardware debugger, DoCD, which enables easy software debugging and validation.
The DF6811E is a silicon proven and fully customisable solution. DCD delivers it in the exact configuration, which allows the licensee to save his time and money (there’s no need to pay extra, for usused features and wasted silicon). The package includes also fully automated test bench with complete set of tests to validate it at each stage of SoC design flow.
Digital Core Design: https://dcd.pl/ipcore/116/df6811e/
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