HDL-based FPGA design and simulation solution
Active-HDL 9.1 supports design creation and simulation of the newest industry-leading FPGA devices from Altera, Atmel, Lattice, Microsemi (Actel), Tabula, Quicklogic and Xilinx.
With design creation, documentation, code coverage and simulation bundled into one product, the latest release of Active-HDL has been integrated with Aldec’s Riviera-PRO verification products, providing a gateway to 64-bit simulation and SystemVerilog Verification. The HDL Code Browser tool enables on-the-fly error detection prior to compilation and the unified coverage database enables designers to manage different types of coverage. Extended documentation support assists users in DO-254 compliance requirements. The tool now supports VHDL-2008 and PSL/SVA assertions. The enhanced level of automation that Active-HDL 9.1 brings within the design creation tools enables customers to save a significant amount of time and detect errors in the source code even before compilation with the new HDL code browser tool. The robust auto-complete technology built into the HDL Editor, language templates and phrase highlighting will enable design teams to quickly and efficiently develop, search and share their HDL code.
More information about Active-HDL 9.1 at https://www.aldec.com/Products/Active-HDL.
Visit Aldec at www.aldec.com
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