Here comes the forksheet transistor, says IMEC

Technology News |
By Peter Clarke

Julien Ryckaert, program director of 3D hybrid scaling, discussed the potential roadmap for transistor development down to 2nm and beyond at the IMEC Technology Forum. He suggested the forksheet could come into deployment at a nominal 2nm node. This would be ahead of the nanosheet-based and vertically staked complementary FET (CFET), another idea that has previously been touted by IMEC (see IMEC presents ‘n-over-p’ complementary FET proposal).

However, there remains uncertainty as to whether any or all of the three remaining leading-edge semiconductor companies will adopt which of these technically demanding and therefore expensive schemes to achieve higher performance-power-area (PPA) trade-offs.

The three companies that remain in the leading-edge logic game are Intel, Samsung and Taiwan Semiconductor Manufacturing Co. Ltd.

The questions over adoption are key because at 1nm IMEC is foreseeing a move to radically different device concepts and new functionalities to meet new applications. To make the adoption of a novel device structure worthwhile it really needs to be more long-lived than a single production node. So a move to the forksheet or the CFET for one generation of miniaturiation may not be economic or provide enough time for the supporting ecosystem to develop.

Natural evolution from fin to fork. Source: IMEC.

So, a company that sticks with incremental improvements on the FinFET could win out over the company that goes for the forksheet or the CFET. On such bets vast fortunes could be won or lost.

Next: Long-lived nodes

That said the 3nm and 2nm nodes are likely to be very long lived with numerous + and ++ enhancements along the way in terms of configurations and materials tweeks.

IMEC was working on the stacked nanowire and nanosheet transistor back in the mid part of this decade and garnered interest from both Samsung and Globalfoundries. Globalfoundries has subsequently dropped out of the leading-edge chip manufacturing race (see GloFo rethinks its future, drops 7nm FinFET) but Samsung has just released its first physical design kit for a nanosheet process at a nominal 3nm node (see Samsung releases PDK for 3nm gate-all-around processes).

TSMC, arguably the most advanced chip manufacturer, has been a leading proponent and adherent of the FinFET and has yet to say anything about deviating from that way of making transistors. TSMC has started manufacturing at a nominal 7nm for leading customers with 6nm and 5nm processes available for design work.

Intel, the one-time leader in semiconductor manufacturing, has seen itself overtaken in the chip miniaturization race. The company appears to have had problems getting processes to yield and is still manufacturing on its 14nm FinFET process – codenamed 1272 – with 10nm FinFET processors now not due until late 2019 and 2020. Intel’s 10nm process is codenamed 1274. The 7nm process, designated 1276 is due to arrive in 2021.

Another consideration is that the extreme cost of miniaturization and effective slowing of Moore’s law to a crawl has forced R&D attention on to various forms of 3D stacking and heterogeneous design partitioning. If the infrastructure matures to support this it may yield (PPA) improvements at much lower development cost, making exotic transistor choices moot.

Roadmap with potential intrusions of germanium and sequential 3D processing. Source: IMEC.

“The FinFET is a 3D structure and the CFET seems to be the ultimate compact CMOS structure,” Ryckaert,” told press at a meeting on ahead of the IMEC Technology Forum in Antwerp. “Traditionally power was provided through the back-end-of-line [higher metal layers in the IC structure] but we may now see a move to buried power rails accessed from the wafer backside,” he added.

Ryckaert portrayed the roadmap as FinFET moving to nanosheet FET or gate-all-around structures for improved electrostatics and variable gate width. P and N transistors would be laterally separated.

Nanosheet would then change to the so-called Forksheet as this would reduce the P and N separation and gate capacitance, although it would see a return to the gate being on three-sides of the channel. Ryckaert said that in a paper exercise IMEC had calculated a 10 percent performance improvement for the forksheet over nanosheet at the same area.

Related links and articles:

News articles:

IMEC presents ‘n-over-p’ complementary FET proposal

Samsung releases PDK for 3nm gate-all-around processes

Forum goes back to the future in Antwerp

IMEC, Cadence tape-out first 3nm test chip


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