High-level-synthesis boosted by faster verification flow

High-level-synthesis boosted by faster verification flow

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By Graham Prophet

Existing High-Level Synthesis (HLS) methodologies, Mentor continues, improve design and verification productivity up to ten-fold; however, the time required to close verification on the resulting RTL can potentially wipe out these gains. This release of the Catapult Platform unifies HLS with an established verification methodology and new tools that enable rapid and predictable RTL verification closure based on C++/SystemC-level verification closure.


This latest Catapult release dds the Catapult formal-based C Property Checker (CPC) tool, which automatically finds bugs prior to synthesis, saving days or weeks of verification debugging time. CPC uses formal analysis to automatically identify and formally prove hard-to-find issues such as uninitialized memory, divide by 0, and array bounds errors in the users’ HLS C++/SystemC model (HLSM). In addition to automatic checks, CPC also formally proves user-written assertions and cover points which complement dynamic simulation providing comprehensive verification of the HLSM.


The latest Catapult release also facilitates easier, faster and more predictable RTL verification closure. It achieves this by removing RTL redundancies, adding new RTL test pins, and synthesizing user assertions and cover points in the HLSM into SVA (SystemVerilog Assertions). To reach functional coverage closure more quickly, Catapult also generates a complete RTL test environment that re-uses the user’s C++/SystemC testbench comparing to the original HLSM, to automatically verify that the simulation results are equivalent. To achieve 100% RTL structural/code coverage more quickly, Catapult works with the Questa CoverCheck tool in a seamless flow to quickly find and automatically generate waivers for unreachable code that can be safely ignored. For reachable code, the flow enables the user to quickly understand in generated waveforms what is needed for the HLSM to quickly close any remaining holes. This methodology enables verification to reach 100% RTL coverage closure in days after the HLSM is verified.


This release of Catapult HLS advances the standardization of the HLSM language by fully supporting the new Accellera SystemC Synthesizable Subset. In addition, Catapult supports Algorithmic C (AC) Datatypes for arbitrary-length, bit-accurate integers and fixed-point datatypes which provide static bit-precision and fast simulation time needed for both formal and dynamic tools. Mentor has now made AC Datatypes open source and 100% compatible with the SystemC Synthesis standard. Mentor will also be donating them to Accellera for standardization.


NVIDIA reports on their HLS design and verification success in the recent case study entitled “Working Smarter, Not Harder: NVIDIA Closes Design Complexity Gap with High-Level Synthesis”. “By adopting a C++ High-Level synthesis (HLS) flow using Catapult from Mentor Graphics, NVIDIA was able to simplify their code by 5X, reduce the number of CPUs required for regression testing by 1000X, and run 1000X more tests to achieve higher functional coverage of their designs. HLS decreased design time by 50%…” write authors Frans Sijstermans and JC Li. “The success of the video team’s application of HLS resulted in its adoption company-wide for all new NVIDIA designs. When it comes to working smarter, not harder, HLS is the way to go.”


Mentor Graphics;


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