High-performance Chiplet Interface Standardisation finds more support
Winbond joins UCIe Consortium to support high-performance chiplet interface standardisation
By joining the UCIe Consortium, Winbond supports interconnect standardization that simplifies system-on-chip (SoC) design and eases 2.5D/3D back-end-of-line (BEOL) assembly. The UCIe 1.0 specification provides a complete standardized die-to-die interconnect with a high-bandwidth memory interface, facilitating SoC-to-memory interconnection for low latency, low power, and high performance. Ultimately, standardization will power market growth in advanced multichip engines by accelerating the introduction of higher-performing products that deliver increased value for device makers and end users.
Winbond’s 3D CUBE as a Service (3DCaaS) platform gives customers an one-stop shopping service. It includes 3D TSV DRAM (aka CUBE) KGD memory dies and 2.5D/3D BEOL with CoW/WoW optimized for multichip devices, in addition to the consulting service. That is to say; customers can have more completed and comprehensive support from CUBE and with extra value like Silicon-Cap and interposer. Winbond has been committed to providing the best product solution, and by joining the UCIe Consortium is positioned deliver standardized 3D DRAM and 2.5D/3D BEOL services to customers.
“The UCIe specification will enable 2.5D/3D chip technology to realize its full potential in AI applications from the cloud to the edge,” said Hsiang-Yun Fan, DRAM Vice President of Winbond. “This technology has a major role in continuing to raise performance as well as ensuring the affordability of cutting-edge digital services.”
find more information at www.winbond.com
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