High performance MRAM for cache designs

High performance MRAM for cache designs

Technology News |
By Nick Flaherty

Belgian research lab imec has shown a scalable spin-orbit transfer magnetic random-access memory (SOT-MRAM) non-volatile memory device with the best published performance.

The paper at the 2023 International Electron Devices Meeting (IEEE IEDM 2023) details a SOT-MRAM built on a 300mm wafer with a switching energy below 100 femto-Joule per bit and >1015 endurance for last level cache memory applications.

SOT-MRAM is a promising candidate for replacing SRAM as a last-level cache memory in high-performance computing (HPC) applications. The combination of sub-ns switching, almost unlimited endurance and lower standby power than SRAM. SOT-MRAM bit cells can also potentially be made much smaller than SRAM cells, translating into a higher bit packing density.

imec has explored the scaling potential and limitations of single perpendicular SOT-MRAM devices processed on 300mm wafers – the first ever reported study on SOT-MRAM device scalability. The scaling of the SOT-MRAM not only reduces the footprint of the SOT-MRAM cell, but also largely improves the cell’s performance and reliability.  The scaling of the SOT track improves the memory’s endurance, as it reduces Joule heating inside the SOT layer.

The SOT track is a layer made of metal such as tungsten (W) or platinum (Pt) that resides below the magnetic tunnel junction (MTJ) as the actual switching element of the SOT-MRAM device. The SOT track serves as an in-plane current injection layer, which has been introduced to de-couple
read and write paths.

“In conventional SOT-MRAM designs, the area occupied by the SOT track is larger than the actual MTJ pillar footprint to provide sufficient margin for overlay process control,” said Sebastien Couet, program director magnetics at imec.

“But this results in wasted energy, as part of the current flows outside the MTJ area. We scaled SOT-MRAM devices to their extreme, with SOT track and MTJ pillar having comparable dimensions (critical dimension ~50nm). For these devices, we observed a switching energy below 100 femto-Joule (fJ) per bit, i.e., a reduction of 63% compared to conventional designs. This helps address a remaining challenge of SOT-MRAM, which traditionally requires a high current for the write operation.”

“With an endurance beyond 1015 program/erase cycles, we have experimentally validated our assumption that SOT-MRAM cells can have unlimited endurance – an important requirement for cache memories,” he said. “Our data provide valuable input for circuit designers to perform design-technology co-optimization (DTCO) of SOT-MRAM technology at advanced nodes – trading of performance improvement and design margins.”
Future work focuses on material engineering to further reduce the switching energy per bit, and on optimizing bit cell configuration to further shrink the cell area compared to SRAM.

“On the longer term, these learnings will also be transferred to the development of voltage-gated (VG) SOT-MRAM multi-pillar devices – imec’s ultimate solution for high-density embedded memory applications,” said Couet.


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