High-Rise and Elevators in CPU architecture

High-Rise and Elevators in CPU architecture

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By Wisse Hettinga

New concepts explain the Future of Hardware Technologies for Computing

In his keynote speech on the ‘Future of Hardware Technologies’ at the HiPEAC conference in Toulouse, Subhasish Mitra uses ‘high-rise’ and ‘elevators’ to explain his research in new processor architecture. His (and his students) research is focusing on the use of NanoSystems, the realisation of the ‘dream chip’, the N3XT 3D approach – the ultimate integration of the compute part and the memory, overcoming the well known bottle neck to the memory.

The solution they work on is 3D, meaning that the compute and the memory and other logic are brought close, on top of each other, hence the high-rise. But when you are building a high-rise architecture, the data needs to flow ‘up and down’ as well. That is where the ‘elevators’ come in. With 1nm nanotube interconnecting the various layers of the design it will be possible to integrate the various components, to speed up the processing power and minimizing the energy required.

The nanotubes integrated in the design are small tubes made out of graphene. Graphene is a 2d atomic layer with very special electrical specifications. Researchers are finding more and more applications for this ‘wonder’ material.

He also explains that it is not so much to overcome the well known von Neumann limitations in existing processor architectures. Apart from FPGA’s, all other CPU to memory communication will have some of the von Neumann legacy in it and it is up to the researchers to work with that in their benefit. 

Subhasish Mitra is professor at the Stanford University.

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