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High-speed CMOS synchronous DRAMs up to 256-Mb densities in TSOP II package

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By eeNews Europe


Internally configured as four banks of 1M, 2M, or 4M word x 16 bits with a synchronous interface, the SDRs operate from a single +3.3-V (± 0.3V) power supply, and are lead (Pb) and halogen free. Packaged in a 54-pin, 400-mil plastic TSOP II, the new SDRs offer a fast access time from clock down to 4.5ns at a 5ns clock cycle, and clock rates from 143MHz to 20MHz.

Alliance Memory’s SDRs provide programmable read or write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto pre-charge function provides a self-timed row pre-charge initiated at the end of the burst sequence. Easy-to-use refresh functions include auto- or self-refresh, while a programmable mode register allows the system to choose the most suitable modes to maximize performance.

Visit Alliance Memory at www.alliancememory.com


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