High speed inter-chip (HSIC) compatible PHY IP

High speed inter-chip (HSIC) compatible PHY IP

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By eeNews Europe

Implementation of the HSIC technology enables setting up a direct connection on a PCB board between a USB Host chip and other on-board USB devices. The HSIC standard features much less power consumption by eliminating the requirements to support long external USB cables while remaining USB protocol compliant and thus USB software compatible.

Through the implementation of a 240MHz DDR interface the HSIC standard provides full support for the 480Mbps data transfer of the USB protocol. It eliminates the 3.3 and 5V signalling, enabling significant silicon area and power savings in comparison to standard cable USB 2.0 PHYs. The Evatronix USBHSIC-PHY logic macro is available now on the LFoundry 150nm process and can be ported to any technology node from 65 to 180nm.

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