Highly-integrated ‘Any-rate’ clock multipliers with low jitter

Highly-integrated ‘Any-rate’ clock multipliers with low jitter

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By eeNews Europe

These ICs target applications such as enterprise routers and switches, storage area network (SAN) equipment, servers and communications equipment. Microsemi’s new clock generator family is suitable for clocking high-speed transceivers, including 10G, 40G and 100G Ethernet, and supporting many interfaces including Fiber Channel, Infiniband, XAUI and PCI Express.

The MAX24405/10 and MAX24505/10 high-performance clock synthesizers and the MAX24605 and MAX24610 high-performance jitter attenuators deliver jitter as low as 180 femtoseconds to provide spec-compliant timing for high-performance system components and multi-gigabit interfaces. All variants provide any-to-any frequency conversions for clock signals from 10MHz to 750MHz.

“In the last six months, we strengthened our timing and synchronisation portfolio with our first family of clock buffers, highly integrated dual- and single-channel clock generators, and now six high-performance multi-frequency clock synthesis solutions,” said Maamoun Seido, vice president and business unit manager of Microsemi’s timing products. “We continue to focus on accelerating product development programmes across our timing and synchronisation portfolio and aligning our roadmap with industry needs.”

Each product variant integrates two synthesisers and supports two independent frequency families, replacing competing two-chip solutions. The MAX24505 and MAX24510 have on-chip EEPROM for custom configuration allowing designers to easily provide desired clocks immediately after power-up. Features include the ability to generate up to 20 output clock signals in two frequency families with control over each output clock’s signal format, voltage, drive strength, frequency divider and phase, eliminating the need for external support components such as fanout buffers and format converters. The MAX24605/10 jitter attenuators integrate a low-loop-bandwidth digital phase locked loop (DPLL) to filter low-frequency jitter starting at 4Hz. All variants are pin-compatible providing easy migration of clock-tree designs from one platform to another.


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