How a wide choice of peripheral cells influences the performance and cost of analogue/mixed-signal ICs
The common assumption is that real breakthroughs can only be made in big, once-in-a-generation shifts, such as a move from a larger process node to a smaller one. In fact, a comparable big effect can be achieved over time, through the accumulation of many small or incremental improvements. But the potential for such gradual improvement can easily escape notice, because it does not produce a sudden and dramatic change. All too often its importance is not recognised.
This article highlights one example of this. Complex analogue and mixed-signal ICs contain many IO (peripheral) cells which implement the device’s signal and power interfaces to other components. Optimising peripheral cells can provide many small improvements which in aggregate have a big impact on the whole IC’s performance and cost.
So how can designers take advantage of the opportunity for peripheral cell optimisation?
Improvements in peripheral cell libraries
The ongoing improvements in peripheral cell design are the result of continual research and development efforts undertaken by a range of organisations: analogue IC manufacturers, specialist analogue foundry service providers, and third-party providers of analogue and mixed-signal libraries and process development kits (PDKs).
The improvements stem in large part from the interactions that these specialist providers have with customers. In the field of high-performance analogue semiconductors, the most successful chip designs are the result of close collaboration between the IC’s developers, suppliers of analogue and mixed-signal IP, and a specialist analogue foundry.
Every IC developer benefits from the resulting accumulation by IP suppliers and foundries both of knowledge and of IP. In relation to the selection of optimised peripheral cells, this should be available to the chip design team in the form of:
– a comprehensive benchmark PDK, providing access to the peripheral cell IP supported by the designer’s chosen fabrication process (see Figure 1)
– engineering consulting services
A specialist analogue foundry or IP provider will have a much more extensive library of peripheral cell IP for analogue and mixed-signal ICs than a general-purpose foundry can offer. The development efforts in this direction by foundries and IP suppliers have been aimed in part at giving chip designers more choice, so that they can more closely match the specifications of the peripheral cell to the requirements of their design than they can if using a general-purpose foundry’s more restricted library.
But with choice comes complexity. This in turn means that an important function of the consulting service is to support the chip designers in their selection of the optimal IO cells.
Fig. 1: A foundry’s PDK provides a graphical user interface which helps the chip designer navigate through an IO cell library
next; cell library parameters…
Parameters specified in peripheral cell libraries
The choice of peripheral cells in an extensive library can be specified in terms of various parameters. An example of the benefits of choice and optimisation is the specification of dedicated electrostatic discharge (ESD) protection structures. Greater choice of ESD specifications can result in:
– cost advantages – if the designer needs 1 kV of protection but the library only supports a minimum 2 kV, the cell will be larger and more expensive than the application requires
– performance advantages – dedicated protection structures offering the required protection value can provide for optimised internal routing and improved reliability
The so-called SEED method (System Efficient ESD Design) is an effective way to find the best trade-off between analogue performance and protection for system-level ESD-exposed pins. While most IO library cells include ESD protection up to 2 kV, special IO cells featuring ESD protection levels up to 4 kV and 8 kV may be offered to protect specific pins, and to allow the designer to optimise the system-level ESD performance in light of the choice of external discrete components.
Specialist analogue foundries must therefore be able to offer library cells which can be used to achieve a wide range of ESD protection levels (e.g. 500V, 1 kV, 2 kV, 4 kV, 8 kV – see Figure 2). In addition to library cells conforming to the Human Body Model (HBM), as well as to various standards such as MIL-883H method 3015.8, JEDEC JESD22-A114F, JS-001-2012 and the automotive AEC-Q100 standard, speciality analogue foundries should also offer library cells that conform to the Charged Device Model (CDM).
Fig. 2: various levels of ESD protection should be available to analogue IC designers
This combination of protection values and standards compliance alone provides a huge number of possibilities for proper ESD protection. It is also to the advantage of the IC design team if the PDK and library supplier is ISO/TS16949 certified: this means that the ESD protection structures provided may be safely used in the development of automotive ICs and other ICs with high reliability requirements.
A library will also include different types of power and ground pads which may be used to supply the IC. If dedicated peripheral cells supporting different power rails (for example ESD, output driver and internal IO logic rails) are available for various supply voltages, IC designers can again draw benefit from small gains in performance.
next; voltage rails…
In an advanced 0.18 µm or 0.35 µm CMOS process, support should naturally be available for common supply voltages – 1.8V, 3.3V and 5.0V. High-voltage CMOS processes will extend this support to 10V, 20V and 50V. Some can even support 120V and higher voltages. Different voltage levels on the same chip require a separation of the power domains; this can easily be achieved by inserting so-called ‘power cut’ cells (see Figure 3). These power cut cells can be used to split the power rail between a digital and an analogue power domain, between two digital power domains, or between two analogue power domains.
Another parameter in which library providers can offer cell optimisation is in size – a particularly helpful feature in designs with constrained die area specifications. Library vendors should offer so-called ‘pad-limited’ and ‘core-limited’ IO libraries which can be used in the following different scenarios: for ICs with a large number of IO cells and a small core area, pad-limited IOs are the optimal solution to minimise chip area, as these cells have the smallest possible width. Whereas for ICs with a small number of IO cells and a reasonably large core area, core-limited IOs reduce the overall chip area since they have the least possible height.
Specialist foundries and library providers will also be able to offer additional choices, including provision for output buffer cells with various current drive strengths, and IO cells with separated supply buses, lowering noise in sensitive applications.
Fig. 3: Layout example using power cut cells to separate analogue and digital supply
next; multiple metal layers
Multiple metal layers
As stated above, the foundry has a role in advising the chip designer on the choice of IO cells. It should also help the designer to align its choice of cells with the requirements of the chosen process technology, since this introduces another element of complexity. While 0.35-µm analogue and mixed-signal processes typically support three or four metal layers, more advanced 0.18-µm specialist analogue processes include as many as seven layers of metal (see Figure 4).
Depending on the number of metal layers used in the design, product developers have to select the corresponding IO library. The IO cells in the design must include the top metal of the process technology that the design uses. By placing all IO cells next to each other, the designer automatically forms a peripheral ring. All the required protection structures are then automatically connected to the appropriate rings.
Fig. 4: layout example of IO cells with various metal layers
The description of the richness of peripheral cell libraries available from specialist analogue and mixed-signal providers shows that the days are gone when a foundry could simply provide a fabrication service alone for designs developed entirely on the customer’s side. The provision of an optimised IO cell library compatible with a foundry’s fabrication process provides numerous benefits to the chip design team, including:
– saving time through the use of available, off-the-shelf IP
– saving costs by reducing die size
– gaining performance, as optimised IP closely fits the requirements of the design
The use of optimised IP from a library also increases the chance that the chip developer will create a right-first-time design. In addition, any customer-specific or dedicated IO library cell can be rapidly generated with limited effort using state-of-the art software tools. And by basing chip designs on the most advanced and optimised peripheral cells available from specialist analogue and mixed-signal IP providers and foundries, designers and product developers can benefit from cost and performance improvements without having to move from one node to another, and can achieve the best possible product design without compromise.
Advanced analogue and mixed-signal ICs contain a large number of peripheral cells which implement the device’s signal and power interfaces to other components. It is an important task for a speciality foundry service provider to offer a large set of optimised peripheral cells, enabling the design community to achieve a performance boost through the accumulation of many small or incremental improvements, which in aggregate have a big impact on the whole IC’s performance and cost.
In parameters such as ESD protection and support for various power-supply voltages, choice and area optimisation helps the designer reduce cost, save space and improve performance. By closely collaborating with a specialist analogue and mixed-signal foundry service provider, chip designers can benefit from the widest choice of IO cells and from specialist knowledge of the way to select and implement the cells.
About the author
Andreas Wild joined ams AG as an administrative officer responsible for the product engineering laboratory. Moving to the Design Support team in 1996, Andreas was responsible for PDK (‘hitkit’) qualification, distribution and worldwide technical hotline support. Since 2003, he has been working as Marketing Manager in the ams Full-Service Foundry business unit, and is responsible for customers in the US and southern Europe. Andreas, an Austrian citizen, holds a High School Diploma in electronics.
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