How joint qualification of new memory devices helps to improve system quality, as well as chip quality

How joint qualification of new memory devices helps to improve system quality, as well as chip quality

Technology News |
By Julien Happich

For a supplier of high-performance memory devices such as Cypress Semiconductor, this should mean that the obvious path to success is to introduce new technologies which offer higher data throughput and a faster boot time, or which satisfy system manufacturers’ demands for improved electrical specifications and timings.

On the other hand, it is also the duty of automotive design engineers to strive for perfect quality and a zero defect rate. This tends to give rise to a conservative instinct when faced with new technology. In fact, the automotive customer’s typical reaction, on being presented with a new product, is to ask: ‘Do you have experience with this technology? How does it perform in the field? How many parts have been shipped already?’

It can be a dispiriting moment when the semiconductor applications engineer has to tell his or her customer, ‘You would be the first to use it.’

Experience at Cypress Semiconductor, however, suggests that there is a highly effective way for automotive manufacturers to mitigate the risk of using a new semiconductor product, and to take advantage more quickly of the opportunities that technology presents to improve their products’ performance. Joint qualification (JQ) is a set of processes that enable a semiconductor supplier and an automotive customer to collaborate on in-application product qualification for mutual benefit. This article describes the benefits and outlines the main elements of the process.


Worthwhile return on time and effort

The essential difference between JQ and the ordinary product qualification process that semiconductor manufacturers normally implement is that, in JQ, the customer assembles a sample part in a real platform, which then undergoes testing by both the customer and the silicon supplier. For Cypress and its customer, the goal will be to validate not only a qualified memory, but also a complete qualified system.

By contrast, the conventional semiconductor qualification process produces a verified set of quality specifications measured against standard industry parameters and parameters set by the silicon supplier. But the specific application in which a customer intends to use the part could stress the part, or give rise to impaired performance, in ways that are not revealed by the standard qualification process and test platform.

JQ uncovers these potential impairments and risks. It does so by testing known potential problems, and marginal electrical parameters such as critical timings, in a customer’s system, and checks that the problems have been eliminated. What is more, JQ enables the silicon supplier to catch previously unknown problems that arise when the IC’s functions are exercised in a real application. JQ is not only about preventing failures, either: it also offers the potential to optimise system performance, for instance by increasing data throughput between a memory IC and a processor chipset.

So what’s not to like about JQ? The main drawback is obvious: JQ requires time, effort and resources on the part of both the silicon supplier and the automotive manufacturer. But in Cypress’s opinion, this cost is well worthwhile. JQ enables an IC to reach the highest possible level of quality in field usage.


Better prepared for failures

Perhaps an even more important consideration is that, in the unfortunate event that a device fails on deployment, JQ can help the IC supplier to diagnose the problem and resolve it more quickly. When a customer returns a failed device from the field, diagnosis begins – ideally – with the connection of high-performance analysis tools to the device.

Unfortunately, the complex PCBs found in automotive systems such as instrument clusters or infotainment units are typically populated with ICs housed in ball grid array (BGA) packages, the physical design of which is ill suited to deep system investigation. As a result, it is extremely difficult to connect instruments such as logic analysers or oscilloscopes close to a device such as a Flash memory IC, to capture exactly what happened on the memory bus at the moment the failure occurred.

Unfortunately, to prepare a multi-layer PCB for a deep analysis of a device in a BGA package may take several weeks. And this delay is seldom acceptable to the automotive customer which suffered the fault.

When performing a complete JQ, however, a specification for the new customer platform on which the IC is to be tested can be that it must allow a detailed and deep failure analysis to be performed immediately when necessary. This test platform is then available when needed to support the rapid investigation and resolution of failures in the field.

JQs in practice

JQ tests are carried out on a customer’s system. But both the customer and the silicon vendor can each carry out the qualification work in parallel, so that it may be completed faster.

Cypress starts its testing on a customer-supplied system after adding debug capabilities to it. Next, it characterises the memory devices before and after exercising them using automated test equipment (ATE), to detect any effects attributable to the customer’s application or to mechanical, electrical or thermal stress in the customer’s assembly process. Feedback from these tests helps Cypress’s engineering group to refine the product’s design, so that it can release the best possible product in the future.

While checking and testing Cypress devices in the customer’s system, it is crucial to exercise them in a way that is as similar as possible to real-world usage. Comparisons between the real customer system and Cypress’s own worst-case parameters are particularly revealing. Real customer production methods are also often different from those anticipated, and can have unexpected effects on a device’s behaviour.

This information about a device’s behaviour in the real world would not be acquired without JQ, and it allows Cypress to recommend to its customers best practices to maximise the robustness of their systems. It also allows customers to determine the best settings to optimise system performance. JQ also enables Cypress to find mismatches between the customer’s system, and the test system used by Cypress to determine the specifications of important electrical parameters. This helps the customer’s engineers to pinpoint those aspects of their system’s operation in which behaviour might be imperfectly represented by the IC’s datasheet.

Measures for maximizing quality

Of course, the main goal of JQ is to bring to volume production a part that will have the lowest possible failure rate in the field. This means that it is important to use automotive-grade parts that are produced and tested to Production Part Approval Process (PPAP) standards. This guarantees that the part itself will have an extremely low failure rate.

Then, to improve quality at the level of the customer’s system, the part must be tested for all known critical issues found in the customer’s usage of earlier parts based on older technology. This approach creates a test protocol that closely simulates the customer’s application. In addition, new features and potentially marginal parameters need to be tested in the customer’s platform to determine whether either the system environment, or the customer’s usage model, are compatible with the new technology’s features and specifications.

To illustrate this point with an example, recent JQs with Cypress customers have tested in the customer’s system new features such as the fast DDR QuadSPI, or the HyperFlash read function, or the latest parallel NOR features on both 65nm and 45nm Flash technology. JQs have also tested the error code correction (ECC) function, which can eliminate potential bit flips.


Experiences and examples

As noted above, it is crucial to plan for system optimisation and failure analysis by preparing the customer platform to connect to a logic analyser. This is not a standard procedure, but it enables the customer and silicon supplier to react immediately when failures occur.

It is particularly difficult to get access to all pins on the PCB when investigating high pin-count parallel NOR Flash memories, or other high pin-count memories in a BGA package.

Fig. 1: the Cypress Wingboard gives a logic analyser’s probes a way to get to hard-to-reach pins.

The Cypress Wingboard is a useful tool for solving this problem (see Figures 1, 2). A small board similar in size to the Flash BGA package, it is soldered between the PCB and the Flash memory module. This board supports matched impedance connectors (MICTORs) for connecting the device to a logic analyser.

Fig. 2: a Wingboard mounted on a test board. (The Wingboard concept was originally developed by Spansion before it was acquired by Cypress Semiconductor.)

By connecting high-performance test instruments in this way and using other specialist test equipment or tools, a Flash memory supplier can perform various useful investigations:

  • test critical MCU-Flash timings and marginal parameters in the operation of the high-speed interface
  • use critical FFS functions (such as erase suspend, power fail-safe, garbage collection) to catch potential issues arising from interactions between the device’s hardware and software
  • test the operation of new features such as ECC
  • test the application’s operation in terms of both hardware and customer-specific software (see Figure 3)
  • test the system for the effects of stress caused by fabrication steps such as inspection and reflow

In Cypress’s experience, such investigation informs product enhancements which result in improved read data throughput, reduced boot time, and various other performance optimisations.

Fig. 3: test results obtained by using a Wingboard – in this case, a page read on a parallel NOR Flash IC

The JQ process also delivers a number of benefits to OEMs, including improved time-to-market and the ability to quickly ramp up with the latest Flash memory technology. With a well-developed process and investigation methods, system developers can easily check all key performance and quality parameters and catch any potential problems early.

This method also provides a powerful tool for process improvement, allowing designers to reduce system boot time by drawing on the latest technologies and features. All in all, JQ produces best-in-class quality in the customer’s system, and makes it easy for OEMs to develop new platforms based on the latest technology.

To close, here are – drawn from Cypress’s experience – the ten essential elements of a successful joint qualification:

  1. Focus on the known critical parameters first; only then add more at the customer’s request.
  2. Perform MCU-Flash interface timing analysis, and review the timing set-up (boot, fast SDR or DDR read, burst read, page read).
  3. Review typical device usage (program/erase history, sector usage mapping, flash file system, and software usage).
  4. Test Vcc to +100mV over spec. Check noise, and confirm that Vcc is stable.
  5. Test temperature to +5° over spec.
  6. Review design and loading.
  7. Check for bit-flip robustness and ECC.
  8. Evaluate the impact of customer production processes or application usage profiles on bit integrity.
  9. Cycle through program/erase steps.
  10. Test for mechanical stresses arising from fabrication.


About the author:

Marcel Kuba is Worldwide Director of Field Applications Engineering (Automotive) at Cypress Semiconductor –

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