The death of Moore’s Law has been predicted many times, and the slowing of process technology at the 3nm, 2nm and 1nm nodes is a challenge for the industry.
Biostatistician David Burg and environmental researcher Jesse Ausubel have looked at the evolution of the semiconductor industry since the first transistor using biological analysis. They see ten year cycles, with six so far, and at least two more.
Gordon Moore famously observed that the number of transistors in integrated circuits increases exponentially, doubling every 12–24 months. The increase covers two related factors, the integration of larger numbers of transistors and transistor miniaturization. Growth in the number of transistors per unit area, or chip density, allows examination of the evolution with a single measure.
The academics took the sigmoidal S-curves used for population nalaysis and applied this to Intel’s semiconductor roadmap since the days of Fairchild. They found that the density of Intel processors between 1959 and 2013 are consistent with a biphasic sigmoidal curve with characteristic times of 9.5 years. During each stage, transistor density increased at least tenfold within approximately six years, followed by at least three years with negligible growth rates.
“It is clear that technological evolution, hypothesized here to include transistor miniaturization, is discontinuous and that new designs and processes are distributed unevenly through time in ‘innovation waves’. Technological evolution frequently displays these more complex kinetics with a tendency to saturate because of constraining factors, and this pattern is also reported for semiconductor performance,” they said.
“Recently, a new definition of transistor density has been suggested, and we propose to reexamine processor evolution by examining growth in the number of transistors per unit area, accounting for changes in chip size.”
Next: The evolution of Moore’s Law
Part of the problem with Moore’s original analysis is there are two trends that started together originate together but are divergent. During each stage, transistor density increased at least tenfold within approximately six years, followed by at least three years with negligible growth rates. Rapid transistor miniaturization is achieved during only two-thirds of the history of the transistor.
This makes sense from an economic point of view with the need to increase revenue through continued production of products based on established technologies along with the introduction of newer products. This allows economic returns to be realized from the exponentially growing investments in research and development required by each new pulse of advances. Waves of miniaturization (denser and even physically smaller chips) may have multiplied markets as much as the growing chip size measured in units, such as number of transistors.
The emphasis on ‘More than Moore’ with 3D packaging and chiplets allowing the used of more optimised process technologies for high speed memory, communications and analog functions is also an additional factor in boosting the economic returns.
One of the problems with the analysis is that it rests on Intel’s roadmap, which has stalled in recent years.
“Intel ceased reporting transistor counts and die sizes for their products in 2014. For the past five years, only estimates are available for the information needed for this analysis, and these cannot be confirmed by the authors,” said the researchers.
Foundries TSMC and Samsung have continued to push the roadmap forward with gate-all-around (GAA) transistor architectures to address some of the challenges. New materials such as ruthenium and new transistors architectures such as nanosheets and nanoribbons will be able to take chip designs to 2nm and 1nm resoluttions
“Based on the analysis demonstrated here, the next growth impulse in transistor miniaturization is due,” they say. “A strong possibility is the desire for artificial intelligence (AI) to emulate biological intelligence, including capacity to acquire new knowledge from a sequence of experiences to solve progressively more tasks, and to offer empathy and imagination. AI researchers have advanced algorithmically and increasingly demand hardware to process quantities of data and train AI models. Designers embed significant amounts of fast memory in larger and larger chips to handle AI training algorithms requiring huge amounts of communication but relatively easy computation.”
As befits environmental scientists, the analysis looks at the evolution of the transistor.
The transient logistics of CPUs point to the technological advances driving the waves that make up the process. The first commercial planar transistor developed at Fairchild Semiconductor in 1959 was based on the demonstration of the silicon transistor and adaptation of photolithography techniques, both developed at Bell Labs in 1954 and 1955, respectively, as the basis for the first phase. The metal-oxide-semiconductor field-effect transistor (MOSFET), the foundation for all future transistor technology, was patented and commercialized by General Microelectronics in 1964, perhaps accounting for the initiation of the second logistic wavelet.
Silicon gate technology (SGT) was first implemented by Intel and was the precursor for subsequent microprocessors, beginning with the 4004 and 8080 released in 1971 concomitant with the beginning of the third wave. High-density, short-channel MOS (HMOS), patented in 1977, substantially increased transistor density for the 8086 released in 1978. The 80486, which debuted in 1989, allowing substantially more transistors, permitting the integration of complex circuitry, such as 8 kB cache and a floating-point math coprocessor. Deep–UV excimer laser lithography, demonstrated in 1982 was commercially deployed during the 1990s, perhaps indicating the sixth wavelet, since all processors released since 1998 were manufactured based on this technology. The technologies underlying the third and sixth waves were perhaps the most important during transistor evolution, for the development of the industry for two decades each.
The researchers point to Cerebras and the Wafer-Scale Engine with 1.2 trillion transistors as an example of the latest wave. This embeds 400,000 AI-optimized cores (78 times more than the largest GPU), and has 3,000 times more in-chip memory. However this is an increase in ‘die size’ rather than a change in transistor density.
Transistor density evolution of the past decade conforms to a linear trend connoting slow and incremental advances, but also signifying a substantial departure from Moore’s exponential law. “We have concentrated each of the six growth pulses into a single point. The result is a projection that transistor density evolution may indeed saturate, but after one or possibly two more pulses,” they said.
The researchers point to quantum computing as that potential shift. “Each of these technologies has advantages and hurdles that must be overcome to realize a new rapid growth phase. Not the least of the challenges ahead are the underlying economic factors driving an entire industry,” they point out.
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