How to ground and power complex circuits

How to ground and power complex circuits

Technology News |
By eeNews Europe

As electronics applications continue to become more compact, powerful, and versatile, the final system demands and complexities of mobile and stationary devices also are becoming increasingly sophisticated.  This complexity – which demands wireless and wired interconnectivity of analog and digital circuits — requires system engineers to use multiple power rails and mixed disciplines of circuit design.  Circuits with analog and digital signals tend to cause declaration of several ground references,  often leading to a spaghetti-like result, where ideas are distorted and what appear to be solid solutions turn out to be  chaotic failures.

In order to put engineering foundations back into complex systems, it is imperative that power and grounding solutions are proactively engineered in a manner that optimizes performance and heat dissipation while reducing EMI radiation and signal to noise interference.  This article demonstrates how to optimize complex circuits from the point of view of power delivery, improved signal integrity and properly grounded functional blocks to implement the final system.  The focus is on understanding circuit needs and pre-planning for the final system, because the result of those two steps is a project that effectively moves  from the schematic to the final printed circuit board.  By taking the time during the design stage to consider each block of a complex system from the current path and noise susceptibility point of view, then placing blocks and powering circuits based on the simple axiom that current always flows in a loop, the complexity faced by today’s system engineers can be broken down into manageable pieces, and implemented into a final, robust design.

To demonstrate the theory, let’s examine a simple circuit and consider the shown connections.  This basic circuit consists of three elements, a low-drop out (LDO) linear regulator, a micro-processing USB data-to-audio driver, and a speaker.  All are powered by a USB plug connected to some computing host.  In this example, the USB-to-audio driver must be powered by 3.3V.  Since the speaker is powered by the audio driver output, and the audio driver input needs the +3.3V LDO which is powered by the USB connector (+5V), it seems an obvious conclusion to place them on the board just like the schematic in Figure 1(a) shows.

However, with this configuration, the current making the speaker play will create a voltage bounce while it returns to the driver that sourced the current.  That voltage bounce will, in turn, flow back to the LDO and finally to the USB connector.  In this example, the reference voltage converting the USB data to music will bounce at the rate the music plays.  The phase shift due to the speaker inductance will increase the error and this will be compounded by higher volumes due to increased current levels.  The bounce also will cause ripple that will degrade the sound quality from the speaker.

There are a couple of ways to minimize the impact of the ripple current.  One is to reduce the ripple by adding a capacitor (C1)very close to the USB to Audio IC from the VLDO node to the GND pin such that the capacitor is centered between these nodes.  The ripple reduction should be aimed at the frequencies of interest, in this case the audible range <20kHz.  The capacitance should be selected so that the LDO ripple current is reduced until the interference is removed by using the capacitor current equation (1):

This will reduce the ripple to DC.  Then the current only causes a voltage drop, and it will not vary with time as much (∆t from above should be considered as an average of the audible frequency, 12-14kHz).  Error can then be controlled by using wide power and GND connections between each IC to limit the voltage drop (product of current times resistance) governed by Ohms’ Law.

Figure 1 – A simple circuit showing power circuit causes bounce and must return to source

The width of the GND and power lines should be guided by considering the acceptable loss.  Typical 1-oz copper printed circuit boards (PCBs) resistance can be estimated as ~0.5mΩ per square [2].  Since solving such issues cannot always be accomplished by adding capacitors, the root cause could be addressed as shown in Figure 1 (b).  The LDO is placed above the audio driver IC so that the stereo sound current loop avoids the sensitive audio driver GND, thus the GND voltage bounce that occurs does not interfere with the audio driver and only the small ripple is present.  

In the previous example there were only two current loops for the application.  Now, we will move on to a much more complicated example.  The next system considered is a complex system, such as a tablet.  In this example, the tablet will consist of items such as a backlight, touch screen, camera, charging system (USB and Wireless), Bluetooth, Wi-Fi, audio outputs (speaker, headphones), and memory for storing data.  Of course, most of these applications require various voltage supply rails to operate well.    

As can be seen in Figure 2, this system has five power supply rails and two methods of charging the battery, which means that there will be at least five current loops.  But there will be more to consider than just the DC power supplies and the current paths related to each.  There are multiple switching regulators and broadcasting and receiving antenna systems that all need to be coordinated and controlled using the microprocessor.  In order to visualize the power and GND paths that are associated with each power supply and the block they power, it helps to tabulate each supply and load current estimate in order to consider component power ratings and tolerances; determine trace widths; determine sensitivity to voltage drops, noise injection or generation; and limit current loop areas to reduce EMI emissions.

In Figure 2, the main power supply rails have been color-coded, and the current flowing in the respective GND symbols has been matched to the rail that supplies the current.  For example, every component not related to charging the battery (RED) has an end current return to the battery, but the USB to audio IC is powered by the 3.3V BUCK regulator, which is powered by the 5V Boost, then the battery. Therefore, the GND current returns from the audio IC to each regulator in series and then to the battery; the audio IC current does not return straight to the battery.

Figure 2- Typical Mobile Tablet Schematic Blocks

The system shown in Figure 2 runs off of a Lithium-ion battery that is charged by a USB charger or a wireless power transmitter and receiver.  The battery is boosted up to +5V (for the camera zoom motor, +3.3V step-down regulator for microprocessor, audio, and touchscreen), stepped down to +1.2V (for the microprocessor, memory, Bluetooth, and Wi-Fi), and boosted to +7V for camera flash.   Obviously, voltage regulators should be placed near their respective loads, but the form factor of the final product often forces designers to place loads far from power supplies or intermingled around the board.  Each power supply supports multiple loads, so strategic routing and placement has to be used to control current paths and  unintended EMI.  Some important placement considerations include available space, mechanical constraints, acceptable voltage drops along the power and GND rails (the product of load current and number of squares in traces/planes), power supply and GND currents paths, cost (PCB layer count, components), the frequency of digital or analog signals, and the availability of a direct return path from the source.

For the last example, we present a hypothetical final system with mechanical constraints. In such a system, the user interfaces and overall dimensions will control the design. Figure 3 shows a practical placement of each block.

Figure 3 – Typical Mobile Tablet Application Blocks and Placement

In Figure 3, each power supply has been color-coded for clarity.  The most important part of the image is the coloring of the GND return currents. Because multiple power supplies are in series leading to each final load, the GND currents are forced to complete the return paths in the same order they were supplied.  For example, the battery powers the BUCK1.2V regulator, which powers the microprocessor; therefore, the current powering the microprocessor will return directly to the BUCK1.2V regulator GND prior to returning to the battery. The failure to envision the entire current loop and the order in which the paths are completed can often create unstable operation or inadequate GND current returns because they are not properly accounted for and controlled in the layout.

For example, it is easy to imagine a systems engineer placing the Bluetooth and WiFi antennas in the place of the camera and flash. The problem that would result from the reversal of the camera with the WiFi/Bluetooth blocks is that even though the +1.2V power supply would still properly split to provide power to the blocks as needed, the GND return currents of the high frequency WiFi/Bluetooth would now flow directly through and under the microprocessor/memory blocks, thereby injecting the ripple currents and voltage bounces associated with the antennas directly into the high frequency microprocessor GND and memory transactions.  This will result in errors with analog-to-digital conversions of battery temperature, could corrupt the stereo quality to the speaker, impact the camera resolution, and cause memory errors that could lead to lost data.  By comparison, as drawn, the WiFi/Bluetooth power and GND currents would remain separate and in parallel from the BUCK1.2V regulator to each independent load and back to the source (BUCK1.2V in this case), avoiding all of these issues.

Note that each of the above examples assumes a single GND, and they are drawn as a copper plane that is continuous and uninterrupted on one of the PCB layers. This GND plane is shared by all blocks of the circuit instead of partitioning the GND plane or separating it into sub-sections and using components to combine GND planes and control current paths. Intentional placement of blocks has been implemented because this method uses natural current flow to shield circuits from undesired GND bounce. Any trace that carries currents or voltages (positive potential) must have a return path. The return path will flow as close as possible to the positive potential form of the signal, and it will be distributed on the GND plane under the sourcing signal/power rail [1].  

Understanding current flow and the concept of minimizing current loops leads to the obvious conclusion that the single GND method is ideal and preferred as a PCB design approach because it significantly reduces component count, layer count, and potential radiation. Every trace and block will be provided the shortest return path possible on the PCB.  By following this guidance, the system designer will only have to control the PCB design from the perspective of proper trace widths as well as smart placement of components and blocks.  He or she should not have to check every trace or build multiple experimental boards to obtain the correct power, signal, and GND scheme.  An additional advantage offered by single, uninterrupted  GND plane is that the continuity of the plane allows heat developed to spread evenly across the entire PCB surface, resulting in lower operating temperatures.

Any signal (or power supply) used to drive any circuit must be given a proper path to return to its source.  C circuit designers must consider the source and grounding schemes to properly implement a final system solution.  Consideration of the load and the type of load is crucial during the implementation phase to keep current paths that cause voltage bounce controlled.  Placing and locating those current paths in areas of the PCB that can afford GND noise without impacting performance is key to effective and efficient design.

[1] Ott, Henry.  Partitioning and Layout of a Mixed-Signal PCB.  Printed Circuit Design Magazine.  2001 June. Web. 2014 August 13.
[2] Spataro, Vincent.  Counting squares: A method to quickly estimate PWB trace resistance . EDN Network.  2013 April 12. Web. 2014 September 03.

About the author

Nicholaus Smith is an applications engineer at Integrated Device Technology, Inc. with 11+ years of experience working on Analog, Digital, and Power Management circuits and Boards.I frequently design and use PCBs for consumer and industrial high volume production, engineering evaluation, customer demonstration, IC qualification and automatic test equipment.


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