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Huawei proposes vertical transistor for 3D-DRAM

Technology News |
By Peter Clarke


China’s communications equipment giant Huawei has proposed a vertical channel-all-around (CAA) transistor that could be suitable for the construction of 3D-DRAM.

The proposal is contained in a paper to be presented at the 2022 IEEE Symposium on VLSI Technology and Circuits scheduled to take place from June 12 to 17, in Honolulu, Hawaii.

The device is an indium gallium zinc oxide (IGZO) field effect transistor (FET) with layers of IGZO, high-k dielectric hafnium oxide and IZO organized around a vertical column. The IGZO thickness is about 3nm. The HfOx and IZO are about 8nm thick. The channel length – in the vertical direction is 55nm and the critical dimension in-plane is 50nm

The transistor achieves a current density of 32.8microamps/micron at Vth plus 1V with a sub-threshold swing of 92mV/decade.

The authors claim good thermal stability and reliability from -40 degrees C to +120 degrees C and the transistor makes a promising candidate for high-performance 3D DRAM beyond 1-alpha nodes in the future.

Related links and articles:

www.vlsisymposium.org

www.huawei.com

News articles:

Unisantis unveils vertical, capacitor-less DRAM

IBM, Samsung propose vertical FET for better scaling

Semiwise touts benefits of flat field transistor for DRAM


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