Hybrid SoC architecture exploration tool adds FPGA blocks

Business news |
By Nick Flaherty

Simulation tool developer Mirabilis Design is working with S2C on a hybrid SoC architecture exploration solution that reuses available RTL-based blocks to accelerate model construction and speed-up very complex simulations.  The collaboration enables design projects that deploy model-based design methodology to further reduce the time and effort spent on creating complicated custom models of legacy designs.

 As part of this collaboration, Mirabilis Design’s VisualSim architecture exploration solution integrates S2C’s FPGA-based Prodigy Logic System as a functional block.  The seamless integration allows an FPGA prototype to act as a sub-model, and to provide accurate simulation responses, in system exploration.

“Electronic System-Level architecture exploration is an essential solution for SoC product trade-off and validation.  The core technology of VisualSim solution has already lowered the modeling barrier.  If a portion of the SoC is available in RTL, then the modeling effort can be further reduced by reuse,”  said Deepak Shankar, Founder of Mirabilis Design.  “Modeling custom blocks has traditionally been a challenge in creating a system-level model.  The collaboration enables the RTL behaviour to be easily integrated into the ESL model to create a virtual platform.  The model can be simulated to gather metrics on response times, throughput, power consumption and correctness of data values.“

“Design the right product needs to come before design the product right.  As today’s SoC getting increasingly complex, we have observed a large increase of functional design errors related to specifications in recent years,” said Toshio Nakama, CEO of S2C.  “The ability to accurately model the system that comprises of design blocks in various level of abstractions is key to making sure designers are catching specification issues early in design cycles.  We are excited to partner with Mirabilis to offer prototyping users a hybrid SoC architecture exploration methodology.”;

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