HyperBus; a Spansion interface proposal to speed up NOR Flash throughput
The HyperBus interface is introduced along with a family of NOR memory devices implemented in Spansion’s HyperFlash technology. With Hyperbus, these devices provide a read throughput of 333 MBytes/sec. This is more than five times higher than the fastest competitor technology, Quad SPI flash. At the same time, Spansion has reduced the number of I/O pins to one third, compared to parallel NOR memory. The HyperBus interface consist of an 8-pin address/data bus, a 2-signal differential clock, as well as the usual ‘chip select’ and ‘read data strobe’ pins. The low pin count helps reducing the overall system costs, Spansion argues.
The high read throughput will enable much faster boot times. It also allows program execution directly from the flash, reducing the effort for code shadowing and thus the amount of RAM, Spansion explained.
For the start, the company plans to offer three densities – 128 Mbit, 256 Mbit and 512 Mbit. The latter one will be sampling in Q2/2014.
Spansion; www.spansion.com
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