I2C bus interface soft core fully compatible with Philips v. 3.0 specification

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By eeNews Europe

Moreover, The DI2CMS allows master and slave mode, arbitration and clock synchronization, support for multi-master systems, 7-bit and 10-bit addressing formats on the I2C bus, and some other valuable features. The DI2CMS also supports user-defined timings (data setup, start setup, start hold and others). It comes with a simple interface with support for AMBA – APB Bus, Altera – Avalon Bus, Xilinx – OPB Bus. The soft core is technology independent, that’s why a VHDL or VERILOG design can be implemented in a variety of process technologies.

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