IAR and Codasip collaborate on low-power RISC-V processors
IAR Systems® and Codasip have announced their partnership enabling joint customers to build low-power embedded applications based on RISC-V processors. Following this, version 2.11 of IAR Embedded Workbench® for RISC-V now supports the L30 and L50 processors from Codasip. The L30 and L50 are small and energy-efficient low-power embedded processor cores from Codasip, all fully customizable and adaptable to the unique needs of a project.
IAR Embedded Workbench for RISC-V is a complete CC++ compiler and debugger toolchain with everything embedded developers need integrated in one single IDE. Through its excellent optimization technology, IAR Embedded Workbench for RISC-V helps developers ensure the application fits the required needs and optimize the utilization of on-board memory.
“Codasip L30 and L50 RISC-V processors are fully compliant with RISC-V specification allowing customers to choose from a variety of compilation and debug solutions,” said Zdenek Prikryl, Chief Technology Officer, Codasip. “IAR Systems is a market leader in the embedded space and our processors work flawlessly with IAR Embedded Workbench”.
“The Codasip L30 and L50 are powerful additions to the embedded RISC-V ecosystem,” said Anders Holmberg, Chief Technology Officer, IAR Systems. “We are committed to supporting both new and existing technology partners, as well as customers in making the most out of their investments in RISC-V by continuously expanding our RISC-V product portfolio.”
www.iar.com
www.codasip.com
www.riscv.org
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