
IAR Systems, Codasip team for low-power RISC-V applications
IAR Systems is working with processor core and tool developer Codasip on tools for low-power embedded applications based on RISC-V.
Version 2.11 of the IAR Embedded Workbench for RISC-V now supports the L30 and L50 energy-efficient low-power embedded processor cores from Codasip. These cores are fully customizable and adaptable to the unique needs of a project, which requires more detailed integration with the development tools.
IAR Embedded Workbench for RISC-V is a complete C/C++ compiler and debugger toolchain integrated in one single IDE.
- Codasip boosts custom RISC-V performance in latest tool
- Functional safety tools certified on RISC-V
- Codasip, Imperas team for RISC-V processor IP verification
“Codasip L30 and L50 RISC-V processors are fully compliant with RISC-V specification allowing customers to choose from a variety of compilation and debug solutions,” said Zdeněk Přikryl, Chief Technology Officer, Codasip. “IAR Systems is a market leader in the embedded space and our processors work flawlessly with IAR Embedded Workbench.”
“The Codasip L30 and L50 are powerful additions to the embedded RISC-V ecosystem,” said Anders Holmberg, Chief Technology Officer, IAR Systems. “We are committed to supporting both new and existing technology partners, as well as customers in making the most out of their investments in RISC-V by continuously expanding our RISC-V product portfolio.”
www.iar.com/riscv; www.codasip.com.
Related articles
- C/C++ compiler and debugger toolchain supports RISC-V cores
- IAR Systems partners with Andes on RISC-V code optimization
- RISC-V development tools add IEC 61508 and ISO 26262
Other articles on eeNews Europe
- Picocom samples its RISC-V OpenRAN chip
- Top articles in November on eeNews Europe
- US solid state battery deal for European car makers
- Raspberry Pi prepares for IPO
- Europe shows 2nm, quantum technologies at IEDM
