IAR Systems delivers advanced trace for RISC-V
IAR believes that this implementation is the first that combines a pre-integrated trace and debug solution for the RISC-V ISA.
Trace simplifies debug and assists with good coding practices, as well as enabling extended testing and proof of code coverage, which is required to meet some safety standards. The live information on code coverage and updates provided as the program runs allows IAR Embedded Workbench to help developers improve code quality efficiently.
“The expanded trace support in IAR Embedded Workbench for RISC-V brings our proven trace viewer infrastructure from other architectures into the RISC-V ecosystem,” said Thomas Andersson, Product Manager, IAR Systems. “We have been working closely with SiFive to ensure we make use of all features available in SiFive Insight, and thanks to the native probe support, we provide integrated development workflows where the developer is in the driver seat with full control of the application.”
“IAR Systems’ support for SiFive Insight Advanced Trace and Debug Solution will continue to drive adoption of RISC-V in embedded markets across the globe,” said Drew Barbier, Director of Product Marketing, SiFive. “The powerful features of IAR Embedded Workbench, including C/C++ Compiler, C-SPY Debugger, and instruction trace profiling, take full advantage of SiFive’s RISC-V processor portfolio and Insight trace and debug to enable the next-generation of embedded product development.”
The latest version of IAR Embedded Workbench for RISC-V offers support for RV32 and RV32E 32-bit RISC-V cores, as well as many available ISA extensions, such as C for compressed instructions, and F and D for single-precision and double-precision floating points. Future releases of the software will enhance the debug and trace capabilities after RISC-V standardization efforts.
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