IAR Systems partners with Andes on RISC-V code optimization

IAR Systems partners with Andes on RISC-V code optimization

Business news |
By eeNews Europe

IAR Systems provides the C/C++ compiler and debugger toolchain IAR Embedded Workbench while Andes Technology develops high-performance, low-power processors and their associated SoC platforms. The company has created a rich series of 32-bit embedded CPU core families, it provides the RISC-V cores, AndesCore N25(F)/NX25(F) and A25/AX25, with AndeStar V5 instruction extension and Andes Custom Extension (ACE) instruction customization capabilities.

To further boost the performance of these cores in their target applications, and to ensure code density, Andes and IAR Systems now collaborate to support the cores in IAR Embedded Workbench.

“Andes is moving heavily into RISC-V, and we are determined to support their efforts,” says Anders Holmberg, Chief Strategy Officer, IAR Systems. “By providing maximized code speed and minimized code size for Andes powerful RISC-V cores, we will create new possibilities to reduce time to market and ensure high quality applications based on Andes’ RISC-V ISA.”
“We are excited to partner with IAR Systems to bring new capabilities to the RISC-V community,” comments Dr. Charlie Su, CTO and Senior VP, Andes Technology Corporation. “Together, we will offer powerful solutions for Andes V5 extended ISA as well as ACE that will enable our customers to meet the demanding requirements of today’s electronic devices.”
Support for Andes cores will be provided in IAR Embedded Workbench for RISC-V. The toolchain is currently under development and the first version will be available in mid-2019.

Andes Technology –


If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News


Linked Articles