IBM analog AI chip uses phase-change memory
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IBM Research has developed a multicore compute in memory analog chip for machine learning using phase-change memory (PCM) to reduce the power consumption.
The analog compute in memory AI chip was designed and fabricated in 14 nm CMOS with the phase-change memory added in the backend process, reducing the cost of production. The fully integrated chip features 64 AI cores interconnected via an on-chip communication network. It also implements the digital activation functions and additional processing involved in individual convolutional layers and long short-term memory units.
For 8-bit input/output matrix–vector multiplications, in the four-phase (high-precision) or one-phase (low-precision) operational read mode, the chip can achieve a maximum throughput of 16.1 or 63.1 tera-operations per second at an energy efficiency of 2.48 or 9.76 tera-operations per second per watt, respectively.
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The synaptic weights are stored locally in the conductance values of nanoscale PCM resistive memory devices. The material switches between amorphous and crystalline phases, where a lower electrical pulse will make the device more crystalline, providing less resistance, and a higher electrical pulse makes the device more amorphous, resulting in more resistance.
The PCM device records its state as a continuum of values between the amorphous and crystalline states. The memory is non-volatile, so the weights are retained when the power supply is switched off.
Two key challenges needed to be overcome say the researchers in a paper in Nature. The memory arrays need to be able to compute with a level of precision on par with existing digital systems, and they need to be able to interface seamlessly with other digital compute units, as well as a digital communication fabric on the analog AI chip.
The chip was fabricated in IBM’s Albany NanoTech Complex, and is composed of the 64 analog in-memory compute cores (or tiles). Each of these contains 256-by-256 crossbar array of synaptic unit cells. Time-based analog-to-digital converters are integrated in each tile to transition between the analog and digital worlds and each tile includes lightweight digital processing units that perform simple nonlinear neuronal activation functions and scaling operations.
Each tile can perform the computations associated with a layer of a deep neural network (DNN) model. The synaptic weights are encoded as analog conductance values of the PCM devices. A global digital processing unit is integrated in the middle of the chip that implements more complex operations that are critical for the execution of certain types of neural networks. The chip also has digital communication pathways at the chip interconnects of all the tiles and the global digital processing unit.
Seamlessly combining analog in-memory computing with several digital processing units and a digital communication fabric produces input-output matrix multiplications at 400 GOPS/mm2, more than 15 times higher than previous multi-core, in-memory computing chips based on resistive memory, while achieving comparable energy efficiency.
Other PCM compute in memory articles
- Porting TinyML to analog in-memory compute
- ST hints at analog in-memory computing chip
- Hyperdimensional computing helps improved AI fit on PCM
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