IBM reports drift-tolerant multilevel cell PCM

IBM reports drift-tolerant multilevel cell PCM

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Scientists at IBM Research in Zurich, Switzerland, have reported a method to store multiple bits reliably in a phase-change memory cell. The team used four levels (2-bits) per memory cell in a 200 k-cell array implemented in a 90-nm process technology and reported a coding method to overcome the tendency of the material properties to relax over time. The memory cell is of the mushroom type with doped Ge2Sb2Te5 as the phase-change material.
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Phase-change memory is a nonvolatile memory technology based on changing the material phase and electrical resistance of a chalcogenide layer by the use of electrical heating. It has been touted as possible replacement for both flash memory and DRAM but the technology has proved difficult to scale below 90-nm.

Nonetheless IBM stated that: "With a combination of speed, endurance, non-volatility and density, PCM can enable a paradigm shift for enterprise IT and storage systems within the next five years."

The contribution from IBM’s Zurich researchers was to use a modulation coding scheme applied to small clusters of memory cells, to overcome the problem of short-term drift in multi-bit PCM, which causes the stored resistance levels to shift over time, which in turn creates read errors.

In the present work, IBM scientists used four distinct resistance levels, which are due to different amorphous, crystalline proportions between the electrodes, to store the bit combinations 00, 01 10 and 11.

"We apply a voltage pulse based on the deviation from the desired level and then measure the resistance. If the desired level of resistance is not achieved, we apply another voltage pulse and measure again – until we achieve the exact level," said Haris Pozidis, manager of memory and probe technologies at IBM Research Zurich.

However, because of structural relaxation of the atoms in the amorphous state, the resistance increases over time after the phase change, eventually causing errors in the read-out, IBM said. To overcome this IBM applied a coding technique that they claim is tolerant to drift. The technique is based on the fact that, on average, the relative order of programmed cells with different resistance levels does not change due to drift. Therefore by encoding data in a code word that is applied to cluster of memory cells, in this case 7, it is possible to improve the bit error rate at the expense of bit density

IBM reported 1.57 bits per cell with a 1 in 100,000 bit error rate after 37 days at room temperature. This is before the use of conventional error-correction codes that could bring the overall error rate down to levels around 1 in 10^15 or less, which are required for practical memory devices, the authors said in the paper.

Pozadis said: "We don’t believe there is a fundamental limitation. We believe we can extend this to 3-bits, even 4-bits per cell." He confirmed that the use of iterative programming and coding has implications for slower program and read times. There is also a die area penalty, he said because of the use of reference cells and the need to provide encode/decode hardware.

The PCM test chip was designed and fabricated by scientists and engineers located in Burlington, Vermont; Yorktown Heights, New York and in Zurich.

The paper Drift-tolerant Multilevel Phase-Change Memory by N. Papandreou, H. Pozidis, T. Mittelholzer, G.F. Close, M. Breitwisch, C. Lam and E. Eleftheriou, was presented by Pozidis at the IEEE International Memory Workshop held in May 2011 in Monterey, California.

For further information: www.zurich.ibm.com.

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