There are 21 papers that touch on ferroelectric materials and FeFET memory compared with 12 on MRAM and this is despite the success that MRAM has achieved as an embedded non-volatile memory option at leading foundries. Hafnium-oxide has the advantage that it is already in use in semiconductor manufacturing as an insulating dielectric. If comparable or superior performance to MRAM can be obtained and scalability demonstrated it could gain the advantage.
Here is a quick round up for the ferroelectric FET highlights from IEDM. There are that are two sessions – 4 and 18 – devoted to the topic and several other papers spread throughout the program.
Session 4 is on modelling and simulation of ferroelectric switching dynamics and device applications while Session 18 is on ferroelectric memory. The session kicks off with authors from the universities of Florida, Southern California and Boston presenting on a ferroelectric tunnel junction memory based on the interface between single atomic layer graphene and a 4nm-thick layer of the van der Waals material CuInP2S6 (CIPS). Such an FTJ is promising for both NVM applications and neuromorphic computing, the authors claim. By sandwiching the FTJ layer between electrodes it is possible to the modulate the barrier resistence.
At IEDM the authors are due to present simulations of these heterojunctions, verified by laboratory experiments that show a record-high tunneling electroresistance ratio of 6 x 10^7.
Session 18 kicks off with authors from Kioxia – formerly Toshiba Memory – describing a HfO2-based FeFET and ferroelectric tunnel junction and its suitability for reinforcement learning for an in-memory computing architecture.
The final paper (18.6) in the session comes from authors at Ferroelectric Memory GmbH, NamLab, Applied Materials and Globalfoundries Dresden. This looks at how programming can be used to achieve multi-level cells in FeFET memory. There is the additional claim that appropriately selected programming algorithms can improve the FeFET endurance performance and variability for small device geometries. The influence of switching, trapping and de-trapping on the target programming algorithm is presented.
But not all the ferroelectric hafnium oxide papers are memory and paper 26.3 is entitled:
Energy harvesting in the back-end of line with CMOS-compatible ferroelectric hafnium oxide. The authors are from Fraunhofer IPMS Center Nanoelectronic Technologies, Globalfoundries Dresden and Technical University of Dresden. The conclusion is that HfO2-based ferroelectric materials are promising candidates for integrated energy harvesting.
This opens up the possibility of large-area – even wafer-scale – energy harvesters made economically using silicon manufacturing methods or integration on active chips with energy harvested and retained in the BEOL.
Intel is using the antiferroelectric properties of hafnium-zirconium oxide for their dielectric properties, to make superior capacitors for use with 3D embedded-DRAM. The embedded-DRAM requires operating voltage of less than 1.8V and offers retention of more than 1 millisecond with endurance cycling of 10^12 cycles at 80C.
A paper (9.2) from principle authors with Robert Bosch looks at FeFET for use in analog in-memory computing. A memory with crossbar design achieves a claimed record peak performance of 13,714 TOPS/W.
One of the last papers from the conference (paper 40.4) has the legendary Chenming Hu as the last-named author. Chenming Hu is widely regarded as the father of the FinFET revolution when he was CTO at TSMC in the early years of this millenium.
This is essentially an academic paper from the Taiwan Semiconductor Research Institute but it marks the creation of a gate-all-around CMOS and FeFET memory for near-computing computing.
The 66th IEDM is due to be held virtually from 12 to 16 December, due to the Covid-19 pandemic. Early registration end on November 20. Up until then non-members of the IEEE can register for access to the event at a reduced rate of US$330 rising to US$380 thereafter.
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