IEDM: Intel tweaks embedded MRAM for L4 cache
L4 is the highest level of cache on some of Intel’s highest performing CPUs and has previously been implemented as embedded-DRAM.
The research paper record suggests that both Intel and TSMC are on the verge of introducing both MRAM and ReRAM on their respective 22nm FinFET manufacturing processes. Indeed TSMC has at least one customer designing with embedded MRAM (see TSMC embedded MRAM is key to Gyrfalcon AI chip).
Intel’s next paper follows on from the paper on embedded MRAM for 22nm FinFET that Intel reported at IEDM in December 2018 (see IEDM: Intel embeds MRAM in FinFET process).
Scaling of MTJ and reduction of available write current. Source: Intel and IEDM.
Intel researchers will report on 2Mbyte arrays of scaled magnetoresistive transfer junction devices meeting L4 cache specifications. The chips demonstrated a 20ns write time, a 4ns read time and an endurance of 10^12 cycles. The memory retention is one second at a temperature of 110 degrees C. Bit error rates were low enough that they could be detected and corrected with error-correcting code (ECC) techniques, Intel states in the abstract of the paper.
However, Intel does not explicitly reference its 22nm manufacturing process in the abstract. Rather it discusses a scaled MTJ device. The gist of paper is the improved process and stack for L4 cache applications, which require tighter bit-cell pitches, smaller MTJ sizes and reduced current for writing. The paper also discusses the optimization of the material stack to avoid a voltage elevation phenomenon that would otherwise increase the write error rate.
Paper #2.4, “2MB Array-Level Demonstration of STT-MRAM Process and Performance Towards L4 Cache Applications,” J.G. Alzate et al., Intel.
Related links and articles:
News articles:
TSMC to present 5nm CMOS, 22nm STT-MRAM at IEDM
ISSCC: Intel adds embedded ReRAM to 22nm portfolio
Report: TSMC to offer embedded ReRAM in 2019
IEDM: Intel embeds MRAM in FinFET process
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