IEDM: Micron to present DRAM-like non-volatile memory for AI

IEDM: Micron to present DRAM-like non-volatile memory for AI

Technology News |
By Peter Clarke

A paper on a non-volatile ferroelectric memory developed at Micron is scheduled for this year’s International Electron Devices Meeting (IEDM) in December.

A precis of the paper claims the stacked memory can provide faster data movement and accommodate larger neural network models while offering better energy efficiency compared to conventional DRAM.

Paper 15.7, NVDRAM: A 32Gbit Dual Layer 3D Stacked Non-Volatile Ferroelectric Memory with Near-DRAM Performance for Demanding AI Workloads, is due to be presented within a session of the conference focused on generative AI. The lead author is Nirmal Ramaswamy, vice president of advanced DRAM and emerging memory at Micron.

While novel computer architectures such as near-memory compute and processing-in-memory are popular topics for investigation, the Micron researchers assert that there is a near-term opportunity to outfit existing, traditional compute architectures with more efficient memory.

The paper precis cliams this is the world’s first dual-layer, high-performance, 32Gbit stackable and nonvolatile ferroelectric memory technology and Micron has given the technology the oxymoronic label of non-volatile dynamic random access memory (NVDRAM).

Nonetheless the technology shows potential for most applications as well as for AI. It combines the non-volatility and high-endurance nature of ferroelectric memory cells while surpassing the retention performance of NAND flash memory and provides DRAM-like read/write speeds, the advance synopsis claims.

The memory includes a 5.7nm ferroelectric capacitor as the charge retention device within the 1T1C architecture of a traditional DRAM. The memories are stacked with dual-gated polycrystalline silicon transistors as the access control devices.

Scanning electron microphotograph cross-section of a 32Gbit NVDRAM with dual, stacked 1T1C memory layers, fabricated over a CMOS array. Source: IEDM.

To maximize the memory density the stacked double memory layer is laid down on top of a layer of CMOS access circuitry on a 48nm pitch.

As IEDM is a learned conference there is unlikely to be any formal discussion of the commercial introduction of such a memory. But for it to address a “near-term opportunity” it suggests that a go/no-go decision about its introduction has either been taken or is imminent, possibly dependent on feedback following the presentation.

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