The possibility of quantum computing based on fully-depleted silicon-on-insulator (FDSOI) transistors was presented in a plenary talk and two other papers at the International Electron Devices Meeting, held his week in San Francisco, California.
Immediately prior to IEDM, the startup Siquance (Grenoble, France) came out of stealth under its CEO Maud Vinet (see France’s Siquance startup targets ‘European’ quantum computing). Maud Vinet had previously been CEA-Leti’s quantum hardware program director and provided an invited plenary talk to IEDM. In this she presented work done by French research bodies CEA-Leti and CNRS to demonstrate that FDSOI can be used to store spin-based qubits and perform quantum computing. Vinet pointed out that the ability to use an adapted FDSOI process provides access to the very-large-scale integration (VLSI) fabrication and design techniques at low cost.
Siquance proposes to use the spin-state of an electron trapped in a quantum well as its qubit. The quantum well is the FDSOI transistor channel. Silicon spin qubits have a couple of advantages according to Siquance: relatively long electron spin coherence times and the ability to leverage microelectronics know-how for scale-up and co-integration with classical electronics for control.
For now most quantum computing applications are still out of reach because quantum algorithms typically require more than 100 qubits running millions of operations. In her presentation Vinet said: “To provide accurate results, demands a precision below 1 part in a million. . . which is way below the precision any of the physical systems used so far to build qubits. As a consequence, quantum error correction is introduced to turn analog quantum computing into a digital quantum regime.”
Vinet said that the integration of quantum error correction (QEC) with quantum computation has led to the promising fault-tolerant quantum computing (FTQC) framework
“Currently, topological quantum codes, such as surface codes or triangular color codes, are promising candidates for FTQC,” Vinet’s paper reports. However, several challenges remain to be overcome to integrate QEC in practical systems. Silicon qubits are seen as a serious contender to enable large-scale quantum computing and to implement the algorithms needed to create life-changing applications, the paper concludes.
“FDSOI technology with its back-gate provides a way to move the charges away from the interfaces in the qubits on one hand and on the other hand to re-center the Vt of transistors in the control electronics at low temperature. It is thus a unique option to design and fabricate high performance quantum systems-on-chip, (and) CEA-Leti, CEA-IRIG, CNRS Institut Néel and their spin-off, Siquance, are leveraging these FDSOI capabilities to push the quantum computing state-of-the-art in VLSI technologies,” the paper said.
In a contributed paper scientists from CEA-Leti presented a characterization protocol to help monitor devices in operation regime of quantum confinement at low temperature. He paper reported on the use of 300mm automated probers at 300K and 1K to gain knowledge from a qubit.
The paper presents a fast characterization methodology for qubit devices, and reports wafer-level (WL) measurements on qubit-array structures at both 300K and 1K.
The three-step characterization protocol includes: 300K transistor-like metrics that are informative on material quality and process variability; 1K quantum dot metrics in the many-electron regime and qubit metrics at 100mK in the few-electron regime.
The third IEDM paper on the topic is entitled: ‘FDSOI for cryoCMOS Electronics: Device Characterization Towards Compact Model’
In this invited paper CEA-Leti reported that it has developed a strategy to perform electrical characterization at a large range of temperatures down to ultra-low temperature, along with electrical characterization methodologies, such as DC, RF, ultra-fast measurements and high statistics.
This was applied to FDSOI transistors, demonstrating the potential for cryogenic applications. Analytical models also have been developed as the first steps toward a full cryogenic compact model that can be used as basis for design. The availability of an accurate and yet compact model of transistor operation is fundamental to the creation of physical design kits that support engineers to design, simulate and verify integrated circuits.
In the paper it was said that the compact model would soon be available for a commercial process such as 28nm FDSOI.
“This work enables a very comprehensive understanding of FDSOI transistor behaviour down to ultra-low temperature, which should lead to a breakthrough in cryogenic compact modeling,” said Mikael Cassé, lead author. “This approach already has allowed us to optimize the design of FDSOI cryogenic circuits and most of the results can be easily extended to other advanced technologies, including FinFETS.”
The paper reports that wide range of cryogenic applications, such as spatial, high-performance computing and high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperature.
Research into quantum computing has renewed interest in cryogenic electronics, which provides enhanced electrical performance, but also may see the emergence of novel physical phenomena that may impact transistor operation or provide other ways of operation, paper said.
Cryogenic electronics has potential benefits beyond quantum computing. High-performance computing, could improves processor performance by moving operation into the 20K to 77K temperature range. Low-temperature sensor electronics for spatial applications, high-energy physics experiments could also benefit from improved cryogenic electronics.