IEDM targets next-gen memory technologies

IEDM targets next-gen memory technologies

Technology News |
By eeNews Europe

It’s no surprise that many interesting papers are related to non-volatile memory. It seems like there’s been a decades-long wait for flash to crash and a replacement technology emerging to pick up the pieces. As you might expect, this year’s IEDM offers no shortage of papers related to emerging or "next generation" technologies. If you don’t think 3-D NAND is the next generation, you can accuse me of ignoring new technology. But I think with 3-D stacking, flash will be its own replacement.

For those who think of emerging memory as an alphabet soup of RAMs, perhaps more interesting than any of the new technologies described in the IEDM papers might be the corporate dance that has been going on with the various floating-gate NAND replacements.

Since flash memory is ever approaching its demise, let’s start by looking at scaling. Both today’s planar technology and future 3-D cells are covered in the joint Intel-Micron effort titled, "Scaling Directions for 2-D and 3-D NAND Cells."

What really caught my eye in the 2012 IEDM program was the number of presentations by Macronix. Perhaps best remembered as the company that helped spread video game titles to the masses via Nintendo, Macronix will present five IEDM papers on advanced semiconductor technology. Compare that total with a traditional powerhouse like STMicroelectronics with six or major flash player Hynix with three.

The first Macronix paper picks up on the theme of the invited paper. Macronix employed staircase contacts and a split-page bit line layout to produce an eight-layer 3-D NAND with vertical gate structures.

Another Macronix 3-D NAND paper. (“Design Innovations to Optimize the 3-D Stackable Vertical Gate (VG) NAND Flash,”) illustrates how many technologists see 3-D NAND in our near future.

Moving beyond memory, there are three papers related to CMOS platform technology that are definitely worth a look. First is IBM’s 22-nm SOI technology with embedded DRAM. It’s the first time dual stressors have been implemented adding Si:C for electron mobility enhancement in N-channel FETs along with the now commonplace SiGe source/drains for compressive strain-enhanced P-channel operation. If you don’t think SOI technology with eDRAM is enough, IBM tops off their 22-nm platform with 15 levels of metal.

You’re probably thinking “Gaming." IBM probably is too.

Since Intel released its Tri-Gate process for 22 nm, there has been widespread belief that planar technology is at an end. Samsung is looking for ways to keep things going. Take a look at its paper, "Comprehensive Extensibility of 20nm Low Power/ High Performance Technology Platform Featuring Scalable High-k/Metal Gate Planar Transistors with Reduced Design Corner.”

Speaking of extensibility, what would IEDM be without an Intel paper on advanced CMOS technology? Kelin Kuhn and collaborators will present the invited talk entitled, "The Ultimate CMOS Device and Beyond." Intel will provide its take on what remains in the CMOS roadmap and what lies beyond.

The final paper among my picks is an invited talk from Infineon titled, "The Role of Silicon, Silicon Carbide and Gallium Nitride in Power Electronics." It’s only one angle, but power electronics is attracting increased attention with the push for solid-state lighting.

Finally, I’m very interested to hear the pro-fabless view from GlobalFoundries in the wake of some premature announcements of the death of the fabless/foundry business model. Ajit Manocha, CEO, GlobalFoundries, obviously isn’t buying it, given the title of his luncheon address, "Is the Fabless/Foundry Model Dead? We Don’t Think So. Long Live Foundry 2.0!"

By the way, can we make that last use of "2.0" in the semiconductor industry? Web entrepreneurs have already sucked the life out of that meme.

–Don Scansen is a partner at the technology consulting firm IP Research Group.

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