IF receiver IC delivers 385 MHz bandwidth
The IC consists of two, 14-bit ADCs that deliver 1.0 Gsample/s, 750 Msample/s, or 500 Msample/s and various digital signal processing blocks consisting of four wideband digital downconverters (DDCs), a noise shaping quantiser (NSR), and variable dynamic range (VDR) monitoring. It has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. T
his product is designed to support communications applications capable of sampling wide bandwidth analogue signals of up to 2 GHz. The AD6674 is optimised, ADI says, for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The part is ideal for diversity multiband, multimode digital receivers; 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A receivers; DOCSIS 3.0 CMTS upstream receive paths; or HFC digital reverse path receivers.
The AD6674 features JESD204B (Subclass 1) coded serial digital outputs, in-band SFDR of 83 dBFS at 340 MHz (750 Msample/s), and in-band SNR of 66.7 dBFS at 340 MHz (750 Msample/s)
The device provides 1.4 W total power per channel at 750 Msample/s (default settings), noise density of −153 dBFS/Hz at 750 Msample/s, and 1.25 V, 2.5 V, and 3.3 V DC supply operation.
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